High performance silicon contact for flip chip

Details High performance silicon contact for flip chip High performance silicon contact for flip chip

2001-02-08

2004-05-18

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S774000, C257S775000, C257S664000

Reexamination Certificate

active

06737740

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuitry interconnect lines, in particular, to through-wafer, integrated circuitry interconnect lines.
DISCUSSION OF THE RELATED ART
Semiconductor devices are typically fabricated on a wafer which is subsequently tested and separated into individual dies or chips. Individual dies are then packaged. Packaged chips are then assembled together, typically on a printed circuit board (PCB), and electrically interconnected to perform a desired function. The electrical interconnection of separately fabricated chips generally takes place externally of the individual chips. While PCB techniques are useful for bringing together separately fabricated and assembled chips, doing so brings with it some problems which are not so easily overcome. For example, PCBs consume a large amount of physical space compared to the circuitry of the chips which are mounted to them. It is desirable to reduce the amount of physical space required by such PCBs. Further, assuring the electrical integrity of interconnections between chips mounted on PCBs is a challenge. Moreover, in certain applications, it is desirable to reduce the physical length of electrical interconnections between devices because of concerns with signal loss or dissipation and interference with and by other integrated circuitry devices.
A continuing challenge in the semiconductor industry is to find new, innovative, and efficient ways of forming electrical connections with and between circuit devices which are fabricated on the same and on different dies. Relatedly, continuing challenges are posed to find and/or improve upon the packaging techniques utilized to package integrated circuitry devices, particularly as device dimensions continue to shrink.
SUMMARY OF THE INVENTION
The present invention provides coaxial interconnect lines which are more reliable and better accommodate reduced circuitry dimensions and a method of forming such coaxial interconnect lines.
A semiconductive substrate is provided which includes front and back surfaces, and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion. Conductive material is formed proximate at least some of the interior wall portion. This conductive material provides an outer coaxial line component. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.
In a preferred implementation, the inner conductive coaxial line component is formed by forming a first conductive material within the hole. A second material is formed over the first material, with at least the second material being a seed layer. Subsequently, a metal-containing layer is electroplated onto the seed layer.
The substrate may be used as a chip carrier, or the substrate may have circuit components fabricated thereon and itself be formed an integrated circuit chip.


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