High performance semiconductor memory devices having multiple di

Details High performance semiconductor memory devices having multiple di High performance semiconductor memory devices having multiple di

1996-05-24

1998-05-05

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 365 63, G11C 0000

Patent

active

057485470

ABSTRACT:
The long-existing tight pitch layout problems for dynamic random access memory devices have been solved by using a multiple-dimension bit line structure. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

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"A Full Bit Prefetch Architecture for Synchronous DRAM's", by Toshio Sunaga etc. IEEE J. of Solid-st. Circuits. vol. 30. No. 9. p. 998, Sep. 1995.

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