High performance raid-6 system architecture with pattern...

Details High performance raid-6 system architecture with pattern... High performance raid-6 system architecture with pattern...

2006-12-19

2010-02-16

Chace, Christian P (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S770000

Reexamination Certificate

active

07664915

ABSTRACT:
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.

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