High performance pseudo dynamic 36 bit compare

Details High performance pseudo dynamic 36 bit compare High performance pseudo dynamic 36 bit compare

2011-08-09

2011-08-09

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S129000, C711S168000, C711S209000, C711S211000, C711S212000, C711S217000, C711S220000, C365S049100, C365S049170, C365S189070, C365S189080

Reexamination Certificate

active

07996620

ABSTRACT:
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

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