High-performance processor with streaming buffer that facilitate

Details High-performance processor with streaming buffer that facilitate High-performance processor with streaming buffer that facilitate

1998-04-09

2000-01-04

Pan, Daniel H.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711205, 711141, 712210, 712211, G06F 934, G06F 938

Patent

active

060121343

ABSTRACT:
A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.

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