High performance PFET header in hybrid orientation...

Details High performance PFET header in hybrid orientation... High performance PFET header in hybrid orientation...

2007-09-25

2007-09-25

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S027000, C327S544000, C257S369000, C438S199000

Reexamination Certificate

active

11100883

ABSTRACT:
Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG<GND) in active mode. Another embodiment provides a HOT-A high-VTH thick oxide SOI PFET header scheme. A further embodiment provides a HOT-A body biased high-VTH thick oxide SOI PFET header scheme.

REFERENCES:
patent: 6049245 (2000-04-01), Son et al.
patent: 6310487 (2001-10-01), Yokomizo

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