High performance PD SOI tunneling-biased MOSFET

Details High performance PD SOI tunneling-biased MOSFET High performance PD SOI tunneling-biased MOSFET

2002-12-11

2004-01-06

Niebling, John F. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S345000, C257SE27103, C257SE29129, C257SE27155, C257S471000

Reexamination Certificate

active

06674130

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of MOSFETs with particular reference to biasing such devices through tunneling.
BACKGROUND OF THE INVENTION
Mobile and portable electronics have advanced rapidly and there is an increasing demand for high performance and low power digital circuits. The main technology approach for reducing power has been power supply scaling. Power supply scaling needs to be accompanied by threshold voltage reduction in order to preserve low V
t
, device performance. Unfortunately, low V
t
, raises sub-threshold leakage.
One solution known to the prior art has been to tie the gate to the substrate so as to operate the device as a dynamic threshold voltage MOSFET (DTMOS). This is illustrated as a plan view in FIG.
1
A and schematic diagram FIG.
1
B. Seen there is gate pedestal
11
flanked by source and drain
13
and
14
respectively. P+ connector
12
makes a hard connection between the gate
11
and the base
15
. In that configuration, the gate input voltage forward biases the substrate/source junction and causes V
TH
to decrease. But the gate voltage of a DTMOS has to be limited to approximately one diode voltage (−0.7 V at room temperature) to avoid significant junction leakage.
The present invention discloses a solution to this problem which allows an MOS device to operate under power supply voltages larger than 0.7 V.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,261,878 B1, Doyle et al. show a DTMOS process while U.S. Pat. No. 6,118,155 (Voldman) shows another DTMOS process. U.S. Pat. No. 6,268,629 (Noguchi) shows a partially depleted MOS SOI with a tunnel leakage current. U.S. Pat. No. 6,306,691 (Koh) show a DTMOS SOI process.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide an FET device suitable for operation at very low voltage and power.
Another object of at least one embodiment of the present invention has been that said device not be limited to a maximum applied voltage of 0.7 V at room temperature to avoid significant junction leakage.
Still another object of at least one embodiment of the present invention has been to provide a process for manufacturing said device.
These objects have been achieved by eliminating the hard connection between gate and base that is featured in dynamic threshold voltage devices (DTMOS). In its place the present invention introduces a tunneling connection between the gate and the base. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ in an NMOS device (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage. A process for manufacturing the device is also described.


REFERENCES:
patent: 255171 (1882-03-01), Holcombe et al.
patent: 5960265 (1999-09-01), Acovic et al.
patent: 6118155 (2000-09-01), Voldman
patent: 6236088 (2001-05-01), Nielson et al.
patent: 6261878 (2001-07-01), Doyle et al.
patent: 6268629 (2001-07-01), Noguchi
patent: 6306691 (2001-10-01), Koh

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