High performance parallel binary byte adder

Details High performance parallel binary byte adder High performance parallel binary byte adder

1987-06-26

1990-04-03

Clark, David L.

Boots, shoes, and leggings

G06F 750

Patent

active

049146173

ABSTRACT:
A parallel binary byte adder performs addition and subtraction on the individual bytes of an A-operand and a B-operand as well as on the entire A and B operand. An A-operand is input to a special adder circuit. A B-operand is modified in a set up logic circuit, in accordance with the specific operation to be performed, before being input to the special adder circuit. A set/mask logic generates set, mask and carry signals which are further input to the special adder circuit. The special adder circuit includes an auxiliary functions circuit and a pseudo carry circuit for generating a set of variables which are processed by a sum circuit to produce three partial results. The first partial result relates to bits 0-5 of the particular byte being processed, the second relates to bit 6, and the third relates to bit 7. A concatenation of the three partial results produces a final sum or difference of the particular byte or bytes involved.

REFERENCES:
patent: 3683163 (1972-08-01), Hanslip
patent: 4021655 (1977-05-01), Healey et al.
patent: 4542476 (1985-09-01), Nagafuji
patent: 4682303 (1987-07-01), Uya
Computer Arithmetic Principles, Architecture, and Design, Kai Hwang, pp. 84-91.

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