High-performance non-volatile memory device and fabrication...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S314000, C257S316000, C257S321000, C257S403000, C438S152000, C438S176000, C438S267000, C438S522000, C438S694000

Reexamination Certificate

active

06977408

ABSTRACT:
An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transistor within an EEPROM memory cell. A floating-gate protect layer is formed over the floating-gate electrode and a relatively thick cap oxide layer is formed to overlie the floating-gate protect layer and the source and drain regions and gate electrode of the MOS transistor. A doped oxide layer is formed to overlie the cap oxide layer. The cap oxide layer is formed to a thickness sufficient to create strain in the channel region of the MOS transistor, while not having a thickness that could cause poor data retention in the EEPROM memory cell.

REFERENCES:
patent: 5714412 (1998-02-01), Liang et al.
patent: 6051467 (2000-04-01), Chan et al.
patent: 6281545 (2001-08-01), Liang et al.
patent: 2002/0160595 (2002-10-01), Hineman
patent: 2003/0170954 (2003-09-01), Rudeck
Ota, et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS”, pp. 14-17, IEDM Dec. 2002.

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