High performance multilevel cache hierarchy

Details High performance multilevel cache hierarchy High performance multilevel cache hierarchy

2007-07-18

2010-10-05

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000

Reexamination Certificate

active

07809889

ABSTRACT:
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.

REFERENCES:
patent: 6237064 (2001-05-01), Kumar
patent: 6446166 (2002-09-01), Arimilli et al.
patent: 7293141 (2007-11-01), Donley
patent: 2001/0010069 (2001-07-01), Hetherington et al.
patent: 2003/0154345 (2003-08-01), Lyon

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