High performance MOSFET structure having asymmetrical spacer for

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257324, 257335, 257336, 257337, 257338, 257339, 257344, H01L 2910

Patent

active

059527021

ABSTRACT:
A method of fabricating a field effect transistor (FET) having an asymmetrical spacer formation includes the steps of forming a gate oxide and a gate electrode on a semiconductor material of a first conductivity type. The gate electrode includes a first and second side edges proximate first and second regions, respectively, of the semiconductor material. Ions of a second conductivity type are implanted to form lightly doped regions extending at least between the first side edge and the first region and at least between the second side edge and the second region, respectively. Blanket layers of oxide and nitride are then formed on the gate electrode and the semiconductor material. The nitride layer is patterned and a first sidewall spacer is formed in a remaining portion of the nitride layer proximate the second side edge. A second blanket layer of oxide is then formed on the first oxide layer and first sidewall spacer. Lastly, second sidewall spacers are formed in the second oxide layer, wherein a first one of the second sidewall spacers includes oxide of a first lateral dimension proximate the first side edge and wherein a second one of the second sidewall spacers is juxtaposed with the first sidewall spacer to form a composite sidewall spacer of a second lateral dimension greater than the first lateral dimension. A novel FET is disclosed also.

REFERENCES:
patent: 5017979 (1991-05-01), Fujii et al.
patent: 5053840 (1991-10-01), Yoshikawa
patent: 5334870 (1994-08-01), Katada et al.
patent: 5648673 (1997-07-01), Yasuda
patent: 5663586 (1997-09-01), Lin
patent: 5719424 (1998-02-01), Ahmad et al.

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