Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1997-12-31
2002-11-12
Kim, Matthew (Department: 2186)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C711S154000, C711S149000
Reexamination Certificate
active
06480927
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a shared main memory system for use within a large-scale multiprocessor system, and, more specifically, to a high performing, multi-port shared main memory system that includes an expandable number of memory sub-units, wherein all sub-units may be participating in memory operations substantially simultaneously, the main memory further includes an expandable number of dedicated point-to-point interconnections for connecting selected ones of the sub-units each to a different one of the memory ports for transferring data in parallel between the selected sub-units and the memory ports, thereby providing a memory system that is capable of supporting the bandpass requirements of a modern high-speed Symmetrical MultiProcessor (SMP) system, and is further capable of expanding as those requirements increase.
DESCRIPTION OF THE PRIOR ART
Many data processing systems couple multiple processors through a shared memory. The processors may then communicate through the shared memory, and may also be allowed to process tasks in parallel to increase system throughput.
Coupling multiple processors to a single memory system presents several challenges for system designers. The memory system must have an increased bandpass to service the requests from multiple processors in a timely manner. Moreover, since many medium and large-scale multiprocessor systems are modular, and allow for the addition of processors to accommodate an increase in user demands, it is desirable: to provide a memory system that is also capable of expanding to provide an increased memory capacity, and/or to include the capability to receive requests from additional processors. Finally, because many multiprocessor systems include cache memories coupled to one or more of the processors within the system so that multiple copies of the same data may be resident within multiple memories in the system at once, a memory coherency protocol is necessary. A memory coherency protocol ensures that every processor always operates on the latest copy of the data. For example, memory coherency guarantees that a processor requesting a data item from main memory will receive the most updated copy of the data, even if the most recent copy only resides in another processor's local cache.
Often, a memory design satisfies one of these design considerations at the expense of the others. For example, one way to achieve an expandable system is to interconnect one or more processors and their associated caches via a bused structure to a shared main memory. Increased processing capability and expanded memory capacity may be achieved by adding processors, and memory units, respectively, to the bus. Such a bused architecture also makes implementation of a coherency scheme relatively simple. In a bused system, each processor on the bus can monitor, or “snoop”, the bus, to determined if any of the operations of the other processors on the bus are affecting the state of data held locally within their respective cache. However, bused systems of this type do not achieve parallelism. Only one processor may use the bus at a given time to access a given memory module, and thus memory will perform only one operation at once. Moreover, the arbitration required to determined bus usage imposes additional overhead. As a result, memory latency increases as more processors are added to the system. Thus, a single-bus architecture is not a good choice in systems having more than a few processors.
Memory latency may be somewhat reduced by using a multi-port main memory system which interfaces to the processors and their local caches via multiple buses. This allows the memory to receive multiple requests in parallel. Moreover, some multi-port memories are capable of processing ones of these multiple requests in parallel. This provides increased parallelism, but latency is still a problem if the system is expanded so that more than several processors are resident on the same bus. Additionally, this scheme complicates the coherency situation because processors may no longer snoop a single bus to ensure that they have the most recent data within their local caches. Instead, another coherency protocol must be utilized. To ensure memory coherency in a multi-bus system, caches may be required to send invalidation requests to all other caches following a modification to a cached data item. Invalidation requests alert the caches receiving these requests to the fact that the most recent copy of the data item resides in. another local cache. Although this method maintains coherency, the overhead imposed by sending invalidation requests becomes prohibitive as the number of processors in the system increases.
Another approach to balancing the competing interests associated with providing an improved memory system for a parallel processing environment involves the use of a crossbar system. A crossbar system acts as a switching network which selectively interconnects each processor and its local cache to a main memory via a dedicated, point-to-point interface. This removes the problems associated with bus utilization, and provides a much high memory bandpass. However, generally, crossbar systems may not be readily expanded. A single crossbar switching network has a predetermined number of switched cross points placed at intersections between the processors and memory modules. These switched cross points may accommodate a predetermined maximum number of processors and memory modules. Once each of the switched cross points is utilized, the system may not be further expanded. Moreover, such a distributed system poses an increased challenge for maintaining memory coherency. Although an invalidation approach similar to the one described above may be utilized, the routing of these requests over each of the point-to-point interfaces to each of the local caches associated with the processors increases system overhead.
Thus, what is needed is an expandable main memory system capable of supporting a parallel processing environment. The memory system must be capable of receiving, in parallel, and processing, in parallel, a multiple number of requests. The memory system must further be capable of maintaining coherency between all intercoupled cache memories in the system.
OBJECTS
The primary object of the invention is to provide an improved shared memory system for a multiprocessor data processing system,
A further object of the invention is to provide a shared memory system having a predetermined address range that can be divided into address sub-ranges, wherein a read or a write operation may be performed to all of the address sub-ranges substantially simultaneously,
A still further object of the invention is to provide a memory system having multiple ports, and wherein requests for memory access may be received on each of the multiple ports in parallel;
Another object of the invention is to provide a shared memory system having multiple memory ports, and a predetermined address range divided into. address sub-ranges, wherein a data transfer operation may be occurring in parallel between each different one of the memory ports and each different one of the address sub-ranges,
A further object of the invention is to provide a shared memory system having multiple memory sub-units each of which maps to an address sub-range, and leach of which may be performing a memory operation in parallel with all other sub-units, and wherein queued memory requests are scheduled for processing based on the availability of the memory sub-units,
A further object of the invention is to provide a memory system having a predetermined address range that can be divided into address sub-ranges each mapped to a different memory sub-unit, and wherein additional memory sub-units may be added to the system as memory requirements increase;
A yet further object of the invention is to provide an expandable memory system having a selectable number of memory sub-units each for providing a portion of the storage capacity of the memory system and wherein each of the me
Atlass Michael B.
Bartaille Pierre-Michel
Johnson Charles A.
Kim Matthew
Starr Mark T.
LandOfFree
High-performance modular memory system with crossbar... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-performance modular memory system with crossbar..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-performance modular memory system with crossbar... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2956810