Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-10-12
2003-12-02
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S101000, C365S052000, C365S053000
Reexamination Certificate
active
06658530
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to memory subsystems, and more particularly, to add-in memory modules for expanding the amount of memory in a computer system.
2. Description of the Related Art
The demand for more memory in computer systems is ever increasing. This is true for all levels within the memory hierarchy, including registers (within a microprocessor core), cache memory, main memory, and disk storage. Similar to the demand for more memory is the demand for greater speed in processing information. There are several methods for increasing the speeds of computer systems, including implementing faster clock speeds for new microprocessors and system buses. Other methods for increasing the speed of computer systems involve architectural changes, which may be implemented in the design phase of a computer system. One such method is to increase the size of the data bus. Increasing the size of the data bus may allow newer computers to process more information per clock cycle than older computers with smaller data buses. For example, a computer with a 32-bit data bus may be able to process twice as much information per clock cycle as a computer with a 16-bit data bus.
The speed of computer systems may also be increased by implementing larger memories. One such type of memory, as listed above, is a cache memory. A cache is a small memory within a computer system interposed between the registers of a microprocessor and main memory (i.e. random access memory, or RAM). Cache memories may be used to store frequently accessed instructions and/or data. In general, a microprocessor may access these instructions and/or data from a cache memory much faster than from main memory. Cache memories may be divided into hierarchies. For example, an L1 (Level One) cache is typically located nearer to a processor core (thus allowing faster access) than an L2 (Level Two) cache. Often times, an L1 cache will be implemented directly on a microprocessor die, while an L2 cache will be implemented via memory chips separate from the microprocessor. In some instances, a cache memory that is not implemented directly upon a microprocessor die may be upgradeable. In some computer systems, for example, an L2 cache may be implemented in a memory module that may be coupled to a computer system through a connector. This may allow the size of the L2 cache to be increased at a relatively low cost, and may result in a significant performance increase.
In most cases, an increase in the size of either cache memory or main memory will result in a performance gain by a computer system. Typically, the performance gain will be more noticeable when the size of cache memory is increased, although significant performance gains may be realized by increasing main memory as well.
As previously stated, increasing the size of a data bus and the clock speed of a computer system are two other methods of obtaining higher performance. However, these methods may have an adverse impact on the performance of memory modules. Memory modules are typically implemented using small circuit boards with limited area for signal traces. Implementing a larger data bus can present significant difficulties in designing a circuit board for a memory module intended for such computer systems. In addition to traces for data signals, area must be reserved for traces necessary to convey address and control signals to the chips on the module.
Increasing the clock speed of a computer system may present other difficulties. One such difficulty is related to signal integrity. Typically, as the speed of operation increases, the potential for interference between the various signals (sometimes referred to as “crosstalk”) may also increase. Such crosstalk may induce errors into signal lines on a memory module or computer motherboard. In some cases, an error correction subsystem may be able to correct these errors. However, typical error correction subsystems are limited in the number of simultaneous errors they may detect and/or correct. Uncorrected errors may often times lead to undesirable operation of a computer system. Memory modules operating at higher clock speeds with large data bus widths may be especially susceptible to errors induced by crosstalk.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a high performance memory module in accordance with the present invention. In one embodiment, a memory module is produced for use with a computer system having a wide data path (i.e. data bus), such as 144 bits. The memory module may include a plurality of memory chips mounted upon a printed circuit board. A connector is mounted to the printed circuit board for conveying data, address, and control signals between the memory module and the computer system. Signal traces for address signals, which are common to a majority (if not all) memory chips of the module may be routed such that they are located near the center of the connector. By keeping signal traces for the address signals near the center of the connector, their length may be minimized, thereby conserving circuit board area. Conversely, signal traces for data signals may be routed such that they are near the peripheries of the connector. Typically, a given data signal will be specific to only one memory chip of the module. By arranging the data pins in this manner, they may be kept relatively close to the corresponding memory chip.
In various embodiments, signal integrity issues may be addressed by the design of the memory module. In such embodiments, the connector used in the module design includes two rows of signal pins. A plurality of blades is arranged between the rows of signal pins for providing the required power to the memory module. Within each row of signal pins is located a plurality of pins coupled to an electrical ground. In one embodiment, most signal pins (but not all) are located directly adjacent to a ground pin. The large number of ground pins may improve signal integrity by minimizing or eliminating crosstalk between signal pins. The extra number of ground pins may also provide a low resistance current return path from the module to the system ground. This may allow the memory module to operate at higher clock frequencies.
The memory module may, depending on its design, be used to expand cache memories or main memories. Embodiments employing SRAM's (Static Random Access Memories) may be used to expand a cache memory, such as an L2 cache. Similarly, embodiments employing DRAM's (Dynamic Random Access Memories) may be used to expand the capacity of a main memory subsystem.
Thus, in various embodiments, the high-performance memory module may allow the expansion of either cache memory or main memory. The use of a connector with a large number of ground pins may allow the module to operate at higher frequencies while preserving the integrity of the various control, address, and data signals conveyed between the module and a computer system. Furthermore, by keeping the address pins centrally located on the connector, circuit board area may be more efficiently utilized.
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Doblar Drew G.
Krow-Lucal Steven C.
Robertson William L.
Kim Matthew
Kivlin B. Noäl
Li Zhuo H.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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