High performance low pin count bus interface

Details High performance low pin count bus interface High performance low pin count bus interface

1987-05-01

1989-05-09

Griffin, Robert L.

Multiplex communications

Wide area network

Packet switching

H04J 302

Patent

active

048295159

ABSTRACT:
An interface system between a high speed user bus and a system bus is provided to present to the user bus a picture of the data transferred on the system bus every clock cycle of that system bus. The interface system also allows the user bus to transfer data back to the system bus during selected bus cycles. By using a single pin connection to the system bus, the user bus can send communications back to itself by way of the system bus.

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