High performance interconnect architecture for field...

Details High performance interconnect architecture for field... High performance interconnect architecture for field...

2006-04-18

2006-04-18

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07030648

ABSTRACT:
This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

REFERENCES:
patent: 5825203 (1998-10-01), Kusunoki et al.

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