High performance integrated varactor on silicon

Details High performance integrated varactor on silicon High performance integrated varactor on silicon

2000-09-29

2003-02-18

Chaudhuri, Olik (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S197000, C438S379000, C257S595000

Reexamination Certificate

active

06521939

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating Semiconductor devices, and more particularly, to the formation of a high performance varactor on silicon in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
A key building block of a CMOS monolithic transceiver is the Phase Locked Loop (PLL) circuit. PLL performance is largely dependent on the characteristics of the voltage-controlled oscillator (VCO). In turn, the monolithic integration of VCO circuits onto silicon-based radio frequency (RF) integrated circuits depends upon the ability to fabricate high quality on-chip varactors. A varactor is defined as a voltage-variable capacitor.
Silicon has been identified as one of the key materials in meeting the demands of wireless communications applications. Silicon-based integrated circuits represent a mature technology with low fabrication costs and high packing density. However, the difficulty of realizing high quality factor (Q) varactors with large tuning ranges remains a great challenge for silicon-based RF integrated circuit design and fabrication.
Most conventional on-chip, or integrated, varactors are implemented as either reverse-biased p-n junctions or as accumulation-mode MOS capacitors. Reverse-biased p-n junction varactors exhibit a limited tuning range for low supply voltages due to technology scaling and reliability issues. Prior art accumulation-mode MOS capacitor varactors exhibit low Q values.
Referring to
FIG. 1
, a cross-section of a typical MOS varactor is shown. A semiconductor substrate
10
is shown. The semiconductor substrate could comprise either an n-type or a p-type region. A well
17
may be formed in the semiconductor substrate. A drain
15
and a source
16
are formed in the substrate
10
and in the well
17
, if used. A thin gate oxide layer
14
is formed overlying the semiconductor substrate
10
. A gate electrode
18
is formed overlying the thin gate oxide layer
14
. A voltage potential (V
G
) can be applied to the gate electrode while the drain
15
and the source
16
are connected together to form the other electrode. The drain
15
and the source
16
are commonly called the diffusion.
A prior art MOS varactor comprises a drain
15
and the source
16
of n+ diffusions, an n-well
17
, and the p-type substrate
10
. The operation of the MOS varactor is described below. The gate
18
and the drain
15
and source
16
contacts are the controlling electrodes. The device capacitance is given by C=C
0
WL, where W is the gate width, L is the gate length, and C
0
is given by:
C
0
=((1/
C
OX
)+(1/
C
OX
))
−1
in which C
OX
and C
Si
are, respectively, the oxide capacitance and the capacitance of the depletion layer under the gate, per unit area. By applying a positive voltage between the gate
18
and the n-well
17
, the surface is accumulated and the device capacitance equals the oxide capacitance, C
OX
. If the applied voltage is reversed, the surface layer is depleted and the series capacitance decreases. The maximum capacitance, per unit area, of the device corresponds to a heavily accumulated surface and equals C
OX
=∈/t
OX
, where t
OX
is the thickness of the gate oxide layer. On the other side, the minimum value (C
dmin
) is reached when the voltage difference between the electrode equals the threshold voltage. Beyond this point, an inversion layer is formed under the gate. At low frequency, this effect brings the value of the device capacitance close to the oxide capacitance. At high frequency, where the varactor is typically operated, this effect is not seen and the capacitance remains at its minimum value.
Referring now to
FIG. 2
, a top view of a prior art MOS varactor is shown. Here, the gate electrode
18
is shown intersecting a section of the diffusion
15
and
16
. The varactor is formed by the intersection. This varactor forms a one-dimensional cell where the drain and source sides of the capacitor go in a single direction.
Referring now to
FIG. 3
, an equivalent circuit model of the prior art varactor in the accumulation mode is shown. The varactor is modeled as a series of passive components connected in a network. The gate electrode is modeled as a series inductance (L
s
)
50
, a gate resistance (R
g
)
52
, a gate oxide capacitance (C
ox
)
54
, and a semiconductor capacitance (C
si
)
56
. The substrate is modeled as a well capacitance (C
w
)
68
and a well resistance (R
w
)
66
. The drain and source regions are each modeled as a first dimension accumulation layer resistance (R
acc(1)
)
60
and
62
and a first dimension lightly doped drain (LDD) and contact resistance (R
d(1)
)
58
and
64
. The drain and source and the substrate are grounded
72
while the variable voltage is applied to the gate
70
.
Referring now to
FIG. 4
, an equivalent circuit model of the prior art varactor in the depletion mode is shown. The gate is again modeled as a series inductance (L
s
)
50
, a gate resistance (R
g
)
52
, and a gate oxide capacitance (C
ox
)
54
. In depletion, however, the semiconductor capacitance (C
si
)
56
is attached to the substrate rather than the gate. The substrate is also modeled as a well capacitance (C
w
)
68
and a well resistance (R
w
)
66
. The drain and source regions are each modeled as a first dimension lightly doped drain (LDD) and contact resistance (R
d(1)
)
58
and
64
and a first dimension channel-to-S/D depletion capacitance (C
d(1)
)
74
and
76
.
The changes in the equivalent circuit model of the varactor from the accumulation mode (
FIG. 3
) to the depletion mode (
FIG. 4
) reflect the presence of the depletion region underlying the gate oxide layer
14
during depletion mode. The effective series resistance of the prior art MOS varactor in accumulation mode is given by:
R
s
≡R
acc(1)
/2.
The effective series resistance in depletion mode is given by:
R
s
≡R
w
(
C
si
/(
C
si
+2
C
d(1)
))
2
.
The effective series capacitance in the accumulation mode is given by:
C
s
=C
ox
C
si
/(
C
ox
+C
si
).
Finally, the effective series capacitance in the depletion mode is given by:
C
s
=(
C
ox
(
C
si
+2
C
d(1)
))/(
C
ox
+C
si
+2
C
d(1)
).
Several prior art approaches disclose methods to form on-chip varactors in the manufacture of an integrated circuit device. U.S. Pat. No. 5,405,790 to Rahim et al discloses a p-n junction varactor fabricated in a BiCMOS process. U.S. Pat. No. 5,173,835 to Cornett et al teaches a metal-insulator-silicon (MIS) varactor. A metal oxide, such as zirconium titanate, is used for the dielectric insulator. A high resistivity layer is used underlying the insulator to support large depletion regions under negative bias. U.S. Pat. No. 4,170,818 to Tobey, Jr. et al discloses a method to form a voltage reference circuit based on differences in the gate-to-channel barriers between two JFET devices. U.S. Pat. No. 5,854,117 to Huisman et al teaches a method to form a varicap diode p-n junction for use as a varactor. U.S. Pat. No. 4,226,648 to Goodwin et al discloses a method to form a hyper-abrupt varactor diode p-n junction. A. S. Poret et al, “Design of High-Q Varactors for Low-Power Wireless Application using a Standard CMOS Process,” IEEE 1999 Custom Integrated Circuits Conference, teaches a varactor. R. Castello et al, “A +/−30% Tuning Range Varactor Compatible with Future Scaled Technologies,” 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp.34-35, June 1998, teaches a varactor. W. Wong et al, “Wide Tuning Range Inversion-Mode Gated Varactor and Its Application on a 2-GHz VCO,” 1999 Symposium on VLSI Circuits Digest of Technical Papers, teaches a varactor. F. Svelto et al, “A Metal-Oxide-Semiconductor Varactor,” IEEE Electron Device Letters vol. 20, no.4, pp.164-166, 1999, teaches a varactor. J. N. Burghartz et al, “Integrated RF Components in a SiGe Bipolar Technology,” IEEE J. Solid State Circuits, vol.32, no.9, pp.1440-1445, 1997, teaches a varactor. T. Soorapanth et

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