High performance flip-chip semiconductor device

Details High performance flip-chip semiconductor device High performance flip-chip semiconductor device

1999-04-12

2001-06-12

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S737000, C257S773000, C257S776000, C257S786000, C257S780000, C257S207000, C257S208000

Reexamination Certificate

active

06246121

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to electronic devices and more specifically to high performance flip-chip semiconductor devices.
BACKGROUND ART
High performance microelectronic or semiconductor devices often use solder bumps (“bumps”) for electrical and mechanical connection to other microelectronic devices or substrates. This connection technology is commonly referred to as “flip-chip” technology.
In the flip-chip technology, a plurality of bumps formed of low melting point metal is provided in a predetermined position (“bump pattern”) on the surface of a semiconductor substrate on which active elements are formed. The semiconductor substrate is then connected to a circuit board or another substrate, such as a flip-chip package. The package includes pads that are the mirror image of the bump pattern on the semiconductor substrate. The semiconductor substrate is connected to the flip-chip package at one time by reflow melting of the bumps.
One of the drawbacks of the conventional flip-chip technology is that for each semiconductor device, a custom bump pattern is provided on the associated semiconductor substrate, which in turn requires a custom package with a custom pad pattern that mirrors the bump pattern on the semiconductor substrate. The requirements for custom packages adversely increase the design cycle time and the cost of using the flip-chip technology.
Attempts have been made in the art to provide generic bump patterns for a semiconductor substrate. However, those attempts have not been very successful as they typically fail to achieve an optimized electrical performance (i.e., higher speed and lower noise) for a large variety of semiconductor devices. A solution which would provide a generic bump patterns on semiconductor substrates while optimizing the electrical performance of the associated semiconductor devices has been long sought but has eluded those skilled in the art. As the semiconductor industry is moving at an increasing pace to higher performance semiconductor devices, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate.
The present invention provides a flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and optimized electrical performance.
The present invention further provides a flip-chip semiconductor device which includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry; a first power supply wiring and a first ground wiring disposed in the semiconductor substrate; a signal wiring disposed in the semiconductor substrate; and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns and includes a first row, a second row, a third row, a fourth row, a fifth row and a sixth row. The bumps among the first plurality of bumps which are on the first row are those lying on the innermost peripheral portions, and the bumps among the first plurality of bumps which are on the sixth row are those lying on the outermost peripheral portions. The bumps among the first plurality of bumps, which are on a row with a higher number, are set in position with increased spacing outwardly deviated from the innermost peripheral portions. The first plurality of bumps which are lying on the third row of a first column and a second column that is adjacent to the first column are coupled to the first ground wiring, and the first plurality of bumps which are lying on the sixth row of the first and second columns are coupled to the first power supply wiring. The first plurality of bumps which are lying on the third row of a third column that is adjacent to the second column and a fourth column that is adjacent to the third column are coupled to the first power supply wiring, and the first plurality of bumps which are lying on the sixth row of the third and the fourth column are coupled to the first ground wiring.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5379191 (1995-01-01), Carey et al.
patent: 5686764 (1997-11-01), Fulcher
patent: 5814891 (1998-09-01), Hirano
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 5952726 (1999-09-01), Liang

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