High-performance fault tolerant computer system with clock lengt

Details High-performance fault tolerant computer system with clock lengt High-performance fault tolerant computer system with clock lengt

1996-05-02

1998-12-01

Le, Dieu-Minh

Pulse or digital communications

Repeaters

Testing

39520078, 395553, 375356, G06F 112, G06F 1342

Patent

active

058450602

ABSTRACT:
A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

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