High performance energy efficient push pull D flip flop circuits

Details High performance energy efficient push pull D flip flop circuits High performance energy efficient push pull D flip flop circuits

1995-04-21

1996-09-03

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, 327218, H03K 3356

Patent

active

055527388

ABSTRACT:
An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ P-type MOSFETs in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.

REFERENCES:
patent: 5227674 (1993-07-01), Takahashi et al.
patent: 5321399 (1994-06-01), Notani et al.

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