High-performance DMA controller

Details High-performance DMA controller High-performance DMA controller

2001-05-18

2004-08-10

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S033000, C710S058000, C712S225000, C709S241000, C711S108000

Reexamination Certificate

active

06775716

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to DMA (Direct Memory Access) controllers for controlling direct data transfer between memories and, more particularly, to a DMA controller providing high efficiency of data transfer and low power consumption.
BACKGROUND OF THE INVENTION
In a data processing apparatus in which plural devices or memories are connected to a data bus, when performing direct data transfer between the devices or memories, plural DMA transfer requests assigned with priorities are continuously executed to improve the transfer efficiency. There have been known several methods of the DMA transfer, as follows.
For example, Japanese Published Patent Application No. Hei.09-223102 discloses a direct memory access controller (DMA controller) that improves the data transfer efficiency as described above.
FIG. 27
is a block diagram illustrating the DMA controller, and
FIG. 28
is a block diagram illustrating a data processing apparatus including the DMA controller shown in
FIG. 27
as one of components. With reference to
FIGS. 27 and 28
, in a DMA controller
10022
, control data for plural DMA transfers are set in registers (data holding means)
10012
~
10016
, a DMA wait register (priority holding means)
10027
holds the priorities of the plural DMA transfers, and the plural DMA transfers are executed in the order of the priorities held by the DMA wait register
10027
, under control of a control circuit (transfer control means)
10025
. In the DMA controller
10022
, the control circuit
10025
is connected to a CPU
10004
through a DMA access line
10023
. Through the DMA access line
10023
, addresses, data, and a control signal for access of the CPU
10004
to the registers
10012
~
10016
are transferred, and an interruption signal, a request signal, and an acknowledge signal for informing the end of DMA transfer or the like are transferred. The priorities stored in the DMA wait register (priority holding means)
10027
are predetermined on the basis of the input times of the control data of the plural DMA transfers, or the importance of I/O units
10007
as destinations.
Further, there have been known several methods of clock control to realize low power consumption in a data processing apparatus.
For example, Japanese Published Patent Application No. Hei.08-255034 discloses a low power consumption type data processing apparatus that reduces power consumption without changing the design of a control circuit of a LSI as a whole. The construction of this low power consumption type data processing apparatus is shown in FIG.
29
. The data processing apparatus comprises a plurality of functional circuits
30123
~
30125
, clock control gate circuits
30117
~
30119
provided for the respective functional circuits, gate control registers
30105
~
30107
for recording control data that define the operations of the respective gate circuits, and an address decoder circuit
30111
for controlling writing of data into the registers
30105
~
30107
. The registers
30105
~
30107
are allocated to memory map areas of a CPU or the like, and have their own addresses. The address decoder circuit
30111
decodes address values of the respective registers, which are supplied through the address bus
30103
, on the basis of a write enable signal Sen inputted to the circuit
30111
, according to a command from the CPU, and records the control data to the functional circuits, which are supplied through the data bus
30104
, in the registers. The outputs from the registers are used as clock supply control signals Scc for the respective functional circuits
30123
~
30125
, and the gate circuits
30117
~
30199
permit or inhibit supply of clock signals to the functional circuits
30123
~
30125
, on the basis of the clock supply control signals Scc.
Meanwhile, Japanese Published Patent Application No. Hei.08-153387 discloses a FIFO memory that inhibits access according to the number of significant pixels of an input video signal to realize low power consumption. The construction of the FIFO memory is shown in FIG.
30
.
FIG. 30
is a block diagram illustrating the FIFO memory in view of its function. The FIFO memory comprises a memory cell array
40006
into/from which a data signal is written and read; a clock generator
40003
that receives a reset signal RES supplied from the outside, and generates a CLK (bit line clock) for an I/O circuit
40007
and a first clock CLK
1
(word line clock) for a word line pointer
40004
, on the basis of a clock signal CLK
0
supplied from the outside; an address designation means (the I/O circuit
40007
and the word line pointer
40004
) that makes access to the word lines and the bit lines of the memory cell array
40006
on the basis of the CLK and the CLK
1
, respectively; and a control flag generator
40002
that generates a signal to stop the operation of the clock generator
40003
. According to the CLK
1
outputted from the clock generator
40003
, the word line pointer
40004
sequentially designates the word lines
40008
. When the final pointer
40005
outputs a last line access signal PAS
3
indicating access to the last word line
40008
E, to the control flag generator
40002
, the control flag generator
40002
detects the access of the last address on the basis of the last line access signal PAS
3
and a clock COS that is in synchronization with the CLK
1
, and outputs a clock control signal CCNT to the clock generator
40003
according to the timing of the detection. On receipt of the clock control signal CCNT, the clock generator
40003
stops counting of the fundamental clock CLK
0
. That is, the FIFO memory is a special FIFO memory provided with a clock control signal generation means (control flag generator
40002
) which detects the timings to start writing and readout of data from the control signal, starts supply of the clock to the memory cell array
40006
, and detects the last address signal designated by the address designation means (the I/O circuit and the word line pointer) to stop the clock of the clock generator
40003
.
Furthermore, Japanese Published Patent Application No. Hei.7-182857 relates to a microcomputer system, and discloses a method of performing self-refresh control on a DRAM at waiting of a CPU.
FIG. 31
is a block diagram illustrating the construction of the microcomputer system.
With reference to
FIG. 31
, when the microcomputer system is set in the waiting state, a self-refreshing mode is set by a CPU
50001
, and switching is performed from an interval refreshing circuit
50004
to a self-refreshing circuit
50005
by a command from a RAM controller
50003
. Then, under the state where a clock signal to be generated from a clock generator
50002
during normal operation is stopped, the self-refreshing circuit
50005
supplies a control signal to the DRAM controller
50003
to make the DRAM controller
50003
perform self-refreshing.
Furthermore, Japanese Published Patent Application No. Hei.7-169266 discloses a method of performing split control on a memory cell array in a semiconductor memory device.
FIG. 32
is a block diagram illustrating a fundamental structure of a semiconductor memory.
With reference to
FIG. 32
, the semiconductor memory is provided with a plurality of memory arrays
60001
, and when a predetermined memory array
60001
is selected by a memory array selection circuit
60005
, a word line in the selected memory array
60001
is selected according to an address of a first external address signal group. Simultaneously, with respect to the memory arrays
60001
which are not selected, a word line fundamental clock for self-refreshing and a word line fundamental clock for refreshing (/RASF) are outputted from a clock generation circuit
60006
for self-refreshing that is contained in the chip, to select word lines in the unselected memory arrays
60001
. Before a set time at which the memory array
60001
is to be selected, a refreshing stop signal is outputted to stop the refreshing operation compulsorily, whereby re-storage of sufficient charge in the memor

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