Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1998-03-05
2000-12-26
Nguyen, Hiep T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711143, 711146, G06F 1202
Patent
active
061674915
ABSTRACT:
A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in independently selectable positions in selected queues. A write interface for a memory array is also provided that has a queue for receiving data to be written to the array and a selection circuit for placing in the array a contiguous block of received data, the size of the block and its placement being selectable. The write interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable data received from selected queues in independently selectable positions in the memory array.
REFERENCES:
patent: 5375089 (1994-12-01), Lo
patent: 5440523 (1995-08-01), Joffe
LandOfFree
High performance digital electronic system architecture and memo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High performance digital electronic system architecture and memo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance digital electronic system architecture and memo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1006571