Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-06-08
2001-10-09
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S111000, C710S100000, C710S106000, C710S120000
Reexamination Certificate
active
06301637
ABSTRACT:
TECHNICAL FIELD
The present invention relates to high performance data paths for busing data in devices such as direct access storage device controllers.
BACKGROUND ART
A direct access storage device (DASD) is an on-line digital storage device, such as a magnetic disk drive, that allows rapid read and write operations. Often, DASD systems include more than one disk for increased reliability and crash recovery. Such a system can be a redundant array of inexpensive disks (RAID) unit.
In order to meet greater performance demands, DASD controllers must be capable of handling data at increasing rates. Designing multiple very high data rate channels within a DASD controller unit and, specifically, to and from a central cache memory is limited with current parallel bus structures. Such a parallel bus system in shown in FIG.
1
.
One possible solution for increasing the data rate is to make the parallel bus wider by increasing the number of data wires. This results in several difficulties such as a greater number of traces on a printed circuit board (PCB) requiring valuable board real estate, additional driver/receiver pairs, additional connector pins to provide circuit card-to-circuit card interconnection and increased associated electrical power.
Another possible solution for increasing the data rate is to send parallel bus control signals on dedicated wires. These separate signals, called sideband signals, may signal the start of transmission, provide timing, specify intended receivers, request attention, or indicate success or failure. Using sideband signals increases the number of connecting wires and, hence, suffers from the same drawbacks as increasing the number of data wires.
Still another possible solution for increasing the data rate is to increase the clock rate used on an existing parallel bus. However, decreasing the time between clock edges is limited by the physics of parallel connecting devices. In particular, each device has an associated capacitance. The total capacitance is the sum of the individual capacitances and the distributed capacitance of the interconnecting trace. The velocity of propagation of a signal down the bus is inversely proportional to this total capacitance and, therefore, the clock switching speed is directly limited by the total capacitance.
A further possible solution for increasing the data rate is to use a currently available serial protocol for busing data within the DASD controller. Such protocols include SONET (Synchronous Optical NETwork), Fiber Channel, and USB (Universal Serial Bus). However, these protocols were designed primarily for connection between devices and not intradevice busses; and primarily for use with particular interconnection media such as fiber optic cable, coaxial cable, or twisted pairs. Therefore, use in PCB busses results in data transfer rates no greater than 200 megabytes per second, which is below the capabilities achievable using interconnection media for which the existing protocols were designed. Additionally, the latency inherent in these protocols is troublesome and difficult to reduce.
In addition to simply increasing the data rate on a DASD buss, data must be written to two different disks in a RAID
1
system. One solution with current parallel buses is to send the data twice, effectively halving the data transfer rate. Another solution is to provide multiple parallel paths, requiring twice the hardware. Still another solution is to construct a special protocol enabling two recipients to receive the same data, requiring more complex logic in the protocol engine and potential performance degradation.
What is needed is a bus system that can achieve increased data rates without incurring the problems associated with increasing the number of wires, using sideband signals, increasing the clock rate, or using current serial bus protocols. The ability to support RAID
1
should also be provided.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to increase the data transfer rate over existing parallel bus systems.
Another object of the present invention is to require less PCB real estate, fewer driver/receiver pairs, and less interconnections than existing parallel bus systems.
Still another object of the present invention is to develop a bus system with lower cost than existing parallel bus systems.
A further object of the present invention is to support RAID
1
.
In carrying out the above objects and other objects and features of the present invention, a system is provided for busing data in a direct access storage device (DASD) controller serving a plurality of computer elements. The system includes adapters communicating with one of the computer elements, a plurality of memory cards, at least one switch, each switch in communication with each memory card, and a plurality of bidirectional multichannel serial links, each link connecting one adapter to one switch. Each switch can establish at least one path between each adapter connected to the switch and each memory card.
In one embodiment, each switch includes a set of path controls, each path control controlling one direction of the bidirectional multichannel serial link. In a further refinement, the system includes a second plurality of bidirectional multichannel serial links. Each path control is connected to each memory card by at least one of the second plurality of bidirectional multichannel serial links. In yet another refinement, the switch further includes a switch bus interconnecting a set of path controls and a switch arbiter to determine access to the switch bus.
In another embodiment, each adapter can generate a request frame specifying one or both of a read address and a write address, transmit a write frame if the write address is specified, and receive a read frame if the read address is specified. Transmitting a write frame and receiving a read frame happen concurrently if both the read address and the write address are specified in the request frame.
In still another embodiment, each bidirectional multichannel serial link includes a plurality of serial data drivers in the adapter and corresponding serial data receivers in the switch, a set of unidirectional pairs carrying serial data from each serial data driver in the adapter to the corresponding serial data receiver in the switch, a plurality of serial data drivers in the switch and corresponding serial data receivers in the adapter, and another set of unidirectional pairs carrying serial data from each serial data driver in the switch to the corresponding serial data receiver in the adapter.
In a further embodiment, each direction of each bidirectional multichannel serial link includes a plurality of serial data drivers, a serial data receiver in communication with each corresponding serial data driver, a serial clock driver, and a serial clock receiver in communication with the serial clock driver. In a refinement, each direction of each serial link further comprises a group serial transmitter that can input a parallel data value at a slow clock rate, convert the parallel data value into a plurality of serial sequences, generate a fast clock rate from the slow clock rate, transmit each serial sequence using one of the plurality of serial data drivers at a rate determined by the fast clock rate, and transmit a signal corresponding to the fast clock rate using the serial clock driver. A group serial receiver can accept the signal corresponding to the fast clock rate from the serial clock driver, accept the plurality of serial sequences from the plurality of serial data drivers, generate a slow clock rate from the fast clock rate, convert the plurality of serial sequences to a parallel representation of the data value, output the parallel representation of the data value at the slow clock rate, and output a signal corresponding to the slow clock rate. The serial drivers and receivers may be implemented with flat panel display drivers and receivers.
In the preferred embodiment, all of the above embodiments are employed.
The above objects and other objects, features,
Burns William A.
Krull Nicholas J.
Selkirk Stephen S.
Brooks & Kushman P.C.
Ellis Kevin L.
McLean Kimberly
Storage Technology Corporation
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