Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-03-11
2000-12-12
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711112, 711165, 710129, G06F 1200, G06F 1338
Patent
active
061611654
ABSTRACT:
A high performance data path for performing XOR on the fly. A first memory is connected to a first bus and a second memory is connected to a second bus selectively coupled to the first bus. Logic for performing an XOR can be switched into connection with the first and second bus for XORing data in a buffer with the data passed from one of the memories to the other memory. The result is replaced into the buffer to permit successive XORing. When reading from an interrelated group of disks such as a RAID 3 group, the data path permits an N-1 and go mode in which a read does not wait for data from the last disk to retrieve its data sector. If the last disk contains data (as opposed to parity) the data is obtained from the XORed data in the XOR buffer of the high performance data path. For writing data, the XOR on the fly generates the parity sector for writing at the completion of a write to an interrelated group of disks.
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Bailey Brian K.
Everdell Peter
Reeves Elizabeth H.
Solomon Robert C.
Yates Robert
Bataille Pierre-Michel
Cabeca John W.
EMC Corporation
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