High performance cost optimized memory

Details High performance cost optimized memory High performance cost optimized memory

1998-10-09

2002-06-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S230030, C365S233100, C365S222000, C711S154000

Reexamination Certificate

active

06401167

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic systems for data storage and retrieval. More particularly, the invention is directed toward improved methods and structures for memory devices.
2. Description of the Related Art
In any engineered design there are compromises between cost and performance. The present invention introduces novel methods and structures for reducing the cost of memory devices while minimally compromising their performance. The description of the invention requires a significant amount of background including: application requirements, memory device physical construction, and memory device logical operation.
Memory device application requirements can be most easily understood with respect to memory device operation.
FIG. 1
shows the general organization of a memory device. Memory device
101
consists of a core
102
and an interface
103
. The core is responsible for storage of the information. The interface is responsible for translating the external signaling used by the interconnect
105
to the internal signaling carried on bus
104
. The primitive operations of the core include at least a read operation. Generally, there are other operations required to manage the state of the core
102
. For example, a conventional dynamic random access memory (DRAM) has at least write, precharge, and sense operations in addition to the read operation.
For purposes of illustrating the invention a conventional DRAM core will be described.
FIG. 2
is a block diagram of a conventional DRAM core
102
. Since the structure and operation of a conventional DRAM core is well known in the art only a brief overview is presented here.
A conventional DRAM core
202
mainly comprises storage banks
211
and
221
, row decoder and control circuitry
210
, and column data path circuit comprising column amplifiers
260
and column decoder and control circuitry
230
. Each of the storage banks comprises storage arrays
213
and
223
and sense amplifiers
212
and
222
.
There may be many banks, rather than just the two illustrated. Physically the row and column decoders may be replicated in order to form the logical decoder shown in FIG.
2
. The column i/o lines
245
may be either bidirectional, as shown, or unidirectional, in which case separate column i/o lines are provided for read and write operations.
The operation of a conventional DRAM core is divided between row and column operations. Row operations control the storage array word lines
241
and the sense amplifiers via line
242
. These operations control the movement of data from the selected row of the selected storage array to the selected sense amplifier via the bit lines
251
and
252
. Column operations control the movement of data from the selected sense amplifiers to and from the external data connections
204
d
and
204
e
.
Device selection is generally accomplished by one of the following choices:
matching an externally presented device address against an internally stored device address;
requiring separate operation control lines, such as RAS and CAS, for each set of memory devices that are to be operated in parallel; and
providing at least one chip select control on the memory device.
FIG. 3
illustrates the timing required to perform the row operations of precharge and sense. In their abstract form these operations can be defined as
precharge(device, bank)—prepare the selected bank of the selected device for sensing; and
sense(device, bank, row)—sense the selected row of the selected bank of the selected device.
The operations and device selection arguments are presented to the core via the PRECH and SENSE timing signals while the remaining arguments are presented as signals which have setup and hold relationships to the timing signals. Specifically, as shown in
FIGS. 2-4
, PRECH and PRECHBANK form signals on line
204
a
in which PRECHBANK presents the “bank” argument of the precharge operation, while SENSE, SENSEBANK and SENSEROW form signals on line
204
b
in which SENSEBANK and SENSEROW present the “bank” and “row” arguments, respectively, for the sense operation. Each of the key primary row timing parameters, t
RP
, t
RAS,min
, and t
RCD
can have significant variations between devices using the same design and across different designs using the same architecture.
FIG.
5
and
FIG. 6
illustrate the timing requirements of the read and write operations, respectively. These operations can be defined abstractly as:
data=read(device, bank, column)—transfer the data in the subset of the sense amplifiers specified by “column” in the selected “bank” of the selected “device” to the READDATA lines; and
write (device, bank, column, mask, data)—store the data presented on the WRITEDATA lines into the subset of the sense amplifiers specified by “column” in the selected “bank” of the selected “device”; optionally store only a portion of the information as specified by “mask”.
More recent conventional DRAM cores allow a certain amount of concurrent operation between the functional blocks of the core. For example, it is possible to independently operate the precharge and sense operations or to operate the column path simultaneously with row operations. To take advantage of this concurrency each of the following groups may operate somewhat independently:
PRECH and PRECHBANK on lines
204
a;
SENSE, SENSEBANK, and SENSEROW on lines
204
b;
COLCYC
204
f
on line, COLLAT and COLADDR on lines
204
g
, WRITE and WMASK one lines
204
c
, READDATA on line
204
d
, and WRITEDATA on line
204
.
There are some restrictions on this independence. For example, as shown in
FIG. 3
, operations on the same bank must observe the timing restrictions of t
RP
and t
RAS,min
. If accesses are to different banks, then the restrictions of
FIG. 4
for t
SS
and t
PP
may have to be observed.
The present invention, while not limited by such values, has been optimized to typical values as shown in Table 1.
TABLE 1
Typical Core Timing Values
Symbol
Value (ns)
t
Rp
20
t
RAS,Min
50
t
RCD
20
t
PP
20
t
SS
20
t
PC
10
t
DAC
 7
FIG. 7
shows the permissible sequence of operations for a single bank of a conventional DRAM core. It shows the precharge
720
, sense
721
, read
722
, and write
723
, operations as nodes in a graph. Each directed arc between operations indicates an operation which may follow. For example, arc
701
indicates that a precharge operation may follow a read operation.
The series of memory operations needed to satisfy any application request can be covered by the nominal and transitional operation sequences described in Table 2 and Table 3. These sequences are characterized by the initial and final bank states as shown in FIG.
8
.
The sequence of memory operations is relatively limited. In particular, there is a universal sequence:
precharge,
sense,
transfer (read or write), and
close.
In this sequence, close is an alternative timing of precharge but is otherwise functionally identical. This universal sequence allows any sequence of operations needed by an application to be performed in one pass through it without repeating any step in that sequence. A control mechanism that implements the universal sequence can be said to be conflict free. A conflict free control mechanism permits a new application reference to be started for every minimum data transfer. That is, the control mechanism itself will never introduce a resource restriction that stalls the memory requester. There may be other reasons to stall the memory requester, for example references to different rows of the same bank may introduce bank contention, but lack of control resources will not be a reason for stalling the memory requestor
TABLE 2
Nominal Transactions
Initial
Final
Transaction
Operations
Bank State
Bank State
Type
Performed
closed
closed
empty
sense,
series of column
operations,
precharge
open
open
miss
precharge,
sense,
series of column
operations
hit
series of column
operations
TABLE 3
Transitional Transactions
Initial
Final
Transaction
Operations
Bank State
Bank St

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