Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-05-02
2006-05-02
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
07039836
ABSTRACT:
A cellular computer system is constructed of a plurality of cells. Each cell has a memory system, a plurality of processors capable of accessing the memory system, a system communication interface coupled to processors, and a cell error queue maintained by a processor within the memory system. The system communication interface of each cell is coupled to other cells of the system. A first cell of the plurality of cells is a master cell that maintains a partition error queue and is capable of receiving into the partition error queue error descriptors from the cell error queue of a second cell of the plurality of cells.
REFERENCES:
patent: 5023776 (1991-06-01), Gregor
patent: 6594785 (2003-07-01), Gilbertson et al.
patent: 6701464 (2004-03-01), Austen et al.
patent: 6708291 (2004-03-01), Kidder
patent: 2004/0019835 (2004-01-01), Marisetty et al.
Culter Bradley Gordon
Michaelis Scott Lynn
Powers Richard Dickert
Assessor Brian
Baderman Scott
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