High performance communication controller for processing...

Details High performance communication controller for processing... High performance communication controller for processing...

1999-04-02

2002-10-29

Lee, Thomas (Department: 2185)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S027000, C710S240000, C709S241000, C709S241000

Reexamination Certificate

active

06473808

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to communication controllers, and more particularly to high performance communication controllers.
BACKGROUND OF THE INVENTION
Communication controllers are usually found in networking and telecommunication products. Communication controllers process data streams according to a variety of multi-layered communication protocols, and transform a data packets associated with one communication layer to a data packet associated with another communication layer.
When a communication processor handles data streams associated with a variety of communication protocols, the communication controller handles each communication protocol in a separate mode, and skips between the various modes.
Communication controllers need to handle high speed data streams. Communication controllers further need to handle data streams according to a variety of multi layered communication protocols. In order to handle high speed data streams, communication controllers need to have a very large bandwidth, such as hundreds of MIPS, and even more. In order to receive, transmit and process data according to variety of communication protocols, especially in a very fast manner, communication controller need to skip very quickly between its various modes.
FIG. 1
is a simplified schematic description of old communication channels
1180
, old external memory bank
1100
and old communication controller
101
according to the prior art. Old communication controller
101
is analogues to Motorola's MC68360 chip. Old communication controller
101
comprises of: an old scheduler
1050
, an old first direct memory access controller (i.e.—old first DMA)
1060
, old first memory bank
1070
, old first processor
1090
, old instruction memory bank
1130
, old second processor
1100
and old interface
1160
. Old communication controller
101
is coupled to an old external memory bank
1110
. Old communication controller
101
can also be coupled to other external units, such as but not limited to another external memory bank, a host system and other processors. Old communication controller
101
can be coupled to a plurality of external memory banks. For convenience of explanation, the plurality of memory banks is referred to as old external memory
1110
.
Old scheduler
1050
has inputs
1054
and
1056
and inputs/outputs (i.e.—I/O's)
1052
. Old first DMA
1060
has input
1066
, output
1068
and I/O's
1062
and
1064
. Old first memory bank
1070
has I/O's
1072
,
1074
and
1076
. Old first processor
1090
has input
1095
, output
1096
and I/O's
1092
,
1094
and
1098
. Old second processor
1100
has I/O
1102
. Old external memory bank
1110
has I/O
1116
. Old interface
1060
has I/O's
1162
and
1165
.
N old peripherals PR(
1
)-PR(N)
1141
-
1148
, collectively denoted as
1140
, are coupled to old peripheral bus
1112
. Preferably, N old peripherals
1140
are placed within old communication controller
101
. N peripherals
1140
couple old communication controller
101
to multiple old communication channels CC(
1
)-CC(K)
1181
-
1188
, collectively denoted as
1180
. Old communication channels
1180
have I/O's collectively denoted
1182
. Old peripherals have I/O's collectively denoted
1144
. I/O's
1182
are coupled to I/O's
1144
.
I/O
1142
of old peripherals
1140
, I/O
1072
of old first memory bank
1070
and input
1054
of old scheduler
1150
are coupled to old peripheral bus
1112
. I/O
1062
of old first DMA
1060
, I/O
1116
of old external memory bank
1116
, I/O
1102
of old second processor
1110
, and I/O
1162
of old interface
1160
are coupled to single bus
1113
. Single bus
1113
is an external bus which couples old communication controller
101
to various external units. I/O
1052
of old scheduler
1050
is coupled to I/O
1092
of old first processor
1090
. I/O
1094
of old first processor
1090
is coupled to I/O
1132
of old instruction memory bank
1130
. I/O
1095
of old first processor
90
is coupled to I/O
1165
of old interface
1160
. I/O
1098
of old first processor
90
is coupled to I/O
1076
of old first memory bank
1070
. Output
1096
of old first processor
90
is coupled to input
1066
of old first DMA
100
. I/O
1064
of old first DMA
1060
is coupled to I/O
1074
of old first memory
1070
.
Old interface
1060
is a set of registers which can be accessed by old first processor
1090
, and by any unit which has access to single bus
1113
.
An old peripheral is usually tailored to handle one or more communication protocol. Some old peripherals can be coupled to a single communication channel and some can be coupled to multiple communication channels. One of the peripherals is a Serial Communication Controller (i.e.—SCC), which deals with various communication protocols such as IEEE 802.3/Ethernet, High-Level/Synchronous Data Link Control (i.e.—HDLC/SDLC), Universal Asynchronous Receiver Transmitter (i.e.—UART). Another peripheral is a Serial Management Controller (i.e.—SMC), which deals with UART and provide totally transparent functionality. Another peripheral is a Serial Peripheral Interface (i.e.—SPI) which allows old communication controller
101
to exchange data with other communication controllers and with a number of peripheral devices such as ISDN devices and Analog to Digital converters. The peripherals which deal with serial communication protocols usually are comprised from parallel to serial converters, such as shift register, which receive from a communication channel a serial data bit stream, and convert the bit stream into a set of multiple bit words, to be sent to old first processor
1090
. These peripherals also comprise of parallel to serial converters, such as shift registers, for receiving a multiple bit words from old first processor
1090
and converting each word to a stream of single bits. Conveniently, each old peripheral is a state machine.
Old communication processor
101
could processes data according to a large
20
variety communication protocols. Old communication controller
101
has an old first processor
1090
which can handle a variety of communication protocols, according to programmable routines which can be stored in old instruction memory bank
1130
, old first memory bank
1070
or any other memory bank. When processing data, old first processor
1090
uses a set of parameters (request channel parameters, communication channel parameters) which are stored in old first memory bank
1070
or in old external memory bank
1110
. Conveniently, the parameters are a part of each communication protocol (i.e.—protocol). Usually, the parameters are well known in the art. For example, the Ethernet protocol specific parameters were published at pages 7-247-7-248 of Motorola's MC68360 user's manual, the UART protocol specific parameters were published at page 7-145, the HDLC protocol specific parameters were published at page 7-173, the BISYNC protocol specific parameters were published at page 7-203, and the Transparent protocol specific parameters were published at page. 7-225. There are various types of parameters, such as request channel parameters which define the status of a request channel, and communication channel parameters which define the status of a single communication channel. For example, request channel parameters of a request channel analogues to the SCC were published at page 7-125 of Motorola's MC68260 user's manual, and the communication channel parameters of various communication protocols were published at pages 7-145, 7-173, 7-203, 7-225 and 7-247-7-248 of Motorola's user's manual.
Old second processor
1100
initializes old first processor
1090
and handles high level management and protocol functions, such as byte-swapping, encapsulation and routing. Old first processor
1090
controls all data stream transactions. Old first processor
1090
handles a transaction, after old scheduler
1150
receives a request to handle such a transaction an

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