Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-09
2007-10-09
Ho, Tu-Tu (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S369000, C257S900000, C257SE27108
Reexamination Certificate
active
10604190
ABSTRACT:
A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 3763312 (1973-10-01), Yoneyama
patent: 4256514 (1981-03-01), Pogge
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4648937 (1987-03-01), Ogura et al.
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4729006 (1988-03-01), Dally et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5254866 (1993-10-01), Ogoh
patent: 5291052 (1994-03-01), Kim et al.
patent: 5296401 (1994-03-01), Mitsui et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Askawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5547894 (1996-08-01), Mandelman et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5592007 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5763312 (1998-06-01), Jeng et al.
patent: 5828103 (1998-10-01), Hsu
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5899722 (1999-05-01), Huang
patent: 5905293 (1999-05-01), Jeng et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5989978 (1999-11-01), Peidous
patent: 5994743 (1999-11-01), Masuoka
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6028339 (2000-02-01), Frenette et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6222238 (2001-04-01), Chang et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6245621 (2001-06-01), Hirohama
patent: 6246095 (2001-06-01), Brady et al.
patent: 6248623 (2001-06-01), Chien et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284626 (2001-09-01), Kim
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6512273 (2003-01-01), Krivokapic et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6548877 (2003-04-01), Yang et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6806584 (2004-10-01), Fung et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0106249 (2004-06-01), Huotari
patent: 6-21089 (1994-01-01), None
patent: 09-283760 (1997-10-01), None
patent: 9-283760 (1997-10-01), None
Huang et al., Jun. 3, 2004, United States Patent Application Publication, pp. 1-2.
Novel Locally Strained Channel Technique for High Performance 55nm CMOS K. Ota, et al. 2002 IEEE, 2.2.1-2.2.4, IEDM 27. Local Mechanical-Stress Control (LMC): A New Technique for CMOS—Performance Enhancement A. Shinizu, et al. 2001 IEEE, 19.4.1-19.4.4, IEDM 01-433.
Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design Shinya Ito, et al. 2000 IEEE, 10.7.1-10,7.4, IEDM 00-247. A Highly Dense, HIgh-Performance 130nm node CMOS Technology for Large Scale System -on-a- Chip Applications F. Ootsuka, et al. 2000 IEEE, 23.5.1-23.5.4, IEDM 00-575.
NMOS Drive Current Reduction Caused by Transistor-Layout and Trench Isolation Induced Stress Gregory Scott, et al. 1999 IEEE, 34.4.1-34.4.4, IEDM 99-827. Transconductance Enhancement in Deep Submicron Strained-Si n- MOSFETs Kern (Ken) Rim, et al. 1998 IEEE, 26.8.1-26.8.4, IEDM 98-707.
Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFET's K. Rim, et al. 2002 IEEE, 98-99, 2002 Symposium On VLSI Technology Digest of Technical Papers.
Chidambarrao Dureseti
Doris Bruce B.
Ku Suk Hoon
Abate Esq. Joseph P.
Ho Tu-Tu
International Business Machines - Corporation
LandOfFree
High performance CMOS device structures and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High performance CMOS device structures and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance CMOS device structures and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3845358