High performance CMOS device design

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S288000, C257SE27046, C257SE27108

Reexamination Certificate

active

07465972

ABSTRACT:
A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

REFERENCES:
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6730551 (2004-05-01), Lee et al.
patent: 6881635 (2005-04-01), Chidambarrao et al.
patent: 7238555 (2007-07-01), Orlowski et al.
patent: 2003/0162348 (2003-08-01), Yeo et al.
patent: 2003/0227072 (2003-12-01), Forbes et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 2004/0175872 (2004-09-01), Yeo et al.
patent: 2005/0045905 (2005-03-01), Chu et al.
patent: 2005/0090048 (2005-04-01), Kreps
patent: 2005/0242340 (2005-11-01), Chidambarrao et al.
patent: 2007/0134859 (2007-06-01), Curello et al.
Yin, H., et al., “Fully-Depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGe Buffers,” IEDM, 2003, pp. 53-56.
Yeo, Y.-C., et al., “Enhanced Performance in Sub-100 nm CMOSFETs Using Strained Epitaxial Silicon-Germanium,” IEDM, 2000, pp. 753-756.
Nayak, D. K., et al., “Enhancement-Mode Quantum-Well GexSi1-xPMOS,” IEEE Electron Device Letters, vol. 12, No. 4, Apr. 1991, pp. 154-156.
Ismail, K., et al., “Electron Transport Properties of Si/SiGe Heterostructures: Measurements and Device Implications,” Appl. Phys. Lett., vol. 63, No. 5, Aug. 2, 1993, pp. 660-662.
Kawasaki, H., et al., “Impact of Parasitic Resistance and Silicon Layer Thickness Scaling for Strained-Silicon MOSFETs on Relaxed Si1-xGexVirtual Substrate,” IEEE, 2004, 4 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High performance CMOS device design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance CMOS device design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance CMOS device design will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4035701

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.