High performance CML to CMOS converter

Details High performance CML to CMOS converter High performance CML to CMOS converter

1999-04-14

2001-04-03

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S064000

Reexamination Certificate

active

06211699

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits which use both bipolar and CMOS logic levels. More particularly, the present invention relates to an improved high performance circuit for converting current mode logic (CML) voltage levels to CMOS compatible voltage levels.
BACKGROUND OF THE INVENTION
Integrated circuits which utilize differential bipolar current mode logic (CML) have different voltage ranges with respect to logic high and logic low voltage levels than CMOS technologies. Accordingly, the use of both bipolar and CMOS technologies in a single integrated circuit requires a conversion of current mode logic (CML) differential voltage levels to CMOS compatible voltage level converters or vice versa. For example, it is well known in the art that a typical CML circuit operates with a differential swing of two to three hundred millivolts. In contrast, a typical CMOS circuit operates according to a single ended voltage within a specified voltage range. For example, with a power supply voltage of 3.0 volts, a voltage of 2.5 V to 3.0 V represents a logic high voltage level and a voltage of 0 V to 0.5 V represents a logic low voltage level. As can be readily understood, the combination of CML and CMOS circuitry in a single integrated circuit requires a differential to single-ended conversion and a level conversion.
FIG. 1
a
illustrates the basic circuitry for a prior art CML to CMOS voltage converter. An incoming CML voltage signal is applied across terminals A and AN, with A representing the non-inverted voltage signal and AN representing the inverted voltage signal. The terminal A is coupled to the base of a first npn bipolar junction transistor QN
1
. The collector of the transistor QN
1
is coupled to a first terminal of a resistor R
10
. A second terminal of the resistor R
10
is coupled to a high voltage supply Vcc. The emitter of the transistor QN
1
is coupled to the emitter of a second npn bipolar junction transistor QN
2
. The emitters of each of the transistors QN
1
and QN
2
are coupled to a low voltage supply Vss through a first current source I
S1
. Preferably, the current source I
S1
, is comprised of a NMOS transistor N
100
which is driven by a biasing voltage, V
BIAS
, coupled to the gate of the NMOS transistor N
100
. The base of the transistor QN
2
is coupled to the terminal AN, while the collector of the transistor QN
2
is coupled to a first terminal of a resistor R
20
. A second terminal of the resistor R
20
is coupled to the high voltage supply Vcc. The base of a third npn bipolar junction transistor QN
3
is also coupled to the first terminal of the resistor R
20
and to the collector of the transistor QN
2
. The collector of the transistor QN
3
is coupled to the high voltage supply Vcc, while the emitter of the transistor QN
3
is coupled to the source of a first PMOS transistor T
10
and the source of a second PMOS transistor T
20
. The drain of the first PMOS transistor T
10
is coupled to the gate of the first PMOS transistor T
10
and the gate of a third PMOS transistor T
30
. The drain of the first PMOS transistor T
10
is further coupled to the low voltage supply Vss, through a second current source, I
S2
. The second current source I
2
is comprised of an NMOS transistor N
200
which is driven by the biasing voltage, VBIAS, which is coupled to the gate of the NMOS transistor N
200
. The drain of the second PMOS transistor T
20
is coupled to an output node B. The gate of the second PMOS transistor T
20
is coupled to the gate of a fourth PMOS transistor T
40
and the drain of the fourth PMOS transistor T
40
. The drain of the fourth PMOS transistor T
40
is coupled to the low voltage supply Vss through a third current source, I
S3
. The third current source I
3
is comprised of an NMOS transistor N
300
which is driven by the biasing voltage V
BIAS
, coupled to the gate of the NMOS transistor N
300
. The source of the fourth PMOS transistor T
40
is coupled to the emitter of a fourth npn bipolar junction transistor QN
4
. The collector of the transistor QN
4
is coupled to the high voltage supply Vcc. The base of the transistor QN
4
is coupled to the collector of the transistor QN
1
and the first terminal of the resistor R
10
. The source of the third PMOS transistor T
30
is also coupled to the emitter of the fourth bipolar junction transistor QN
4
. The drain of the third PMOS transistor T
30
is coupled to the drain and the gate of a first NMOS transistor N
10
and the gate of a second NMOS transistor N
20
. The source of the first NMOS transistor N
10
and the source of the second NMOS transistor N
20
are each coupled to the low voltage supply Vss. The drain of the second NMOS transistor N
20
is coupled to the output node B. The output node B drives a CMOS buffer V
10
.
The internal circuitry of the CMOS buffer V
10
is depicted in
FIG. 1
b
. As shown in
FIG. 1
b
, the CMOS buffer V
10
includes a PMOS transistor P
1
having a source connected to the high voltage supply Vcc, a gate coupled to the output node B and a drain coupled to an output node Q. The CMOS buffer V
10
further includes an NMOS transistor N
1
having a drain which is coupled to the output node Q. The gate of the NMOS transistor N
1
is coupled to the output node B and the source of the NMOS transistor N
1
is coupled to the low voltage supply Vss.
Referring again to
FIG. 1
a
, when the differential voltage signal at the terminals A and AN is configured such that A is higher than AN, the transistor QN
1
is turned on, while the transistor QN
2
is off. In this state, an output voltage level measured at the output node B is switched toward the low voltage level Vss. The output voltage at the node B falls to very nearly the level of Vss when the transistor N
20
sinks current out of the node B. As the voltage signal at the terminal A becomes inactive and the voltage signal at the terminal AN goes active, the output voltage at the output node B switches and begins to increase toward the high voltage level Vcc. However, due to the voltage drop associated with the bipolar junction transistors QN
3
, the voltage at the output node B will not reach the same voltage level as Vcc; but, rather, will actually only rise to the level of Vcc less one V
BE
voltage level of the transistor QN
3
and the drain to source saturation voltage level of the transistor T
20
. Typically, this voltage may be as high as 0.8-1.0 volts, depending upon the operating conditions. Because the voltage at the output node B can fall to very nearly the level of Vss, but cannot rise to very nearly the level of Vcc, the voltage level at the output node B will not vary symmetrically with respect to the supply rails Vcc and Vss. This results in different rise and fall times for the voltage at the output Q of the CMOS buffer V
10
because the input threshold of the CMOS buffer V
10
is centered about ½Vcc.
Consider now the CMOS buffer of
FIG. 1
b
. Ideally, when the NMOS transistor N
1
is on, the PMOS transistor P
1
should be off, and the voltage at the output Q will be driven low toward Vss. Conversely, when the PMOS transistor P
1
is on, the NMOS transistor N
1
should be off, and the voltage at the output Q will be driven high toward Vss. However, if the voltage at the node B is not driven high enough, the PMOS transistor P
1
will not be completely turned off when the NMOS transistor N
1
is on. In these circumstances, current will continue to flow through P
1
to the output Q as current is drawn from the output Q through the NMOS transistor N
1
. Under these circumstances, the fall time required for the voltage level at the output Q to reach Vss will take longer than the rise time required for the voltage level at the output Q to reach Vcc. Accordingly, the voltage at the output Q will have an unsymmetrical duty cycle.
When such a prior art CML to CMOS converter is utilized for converting a clock signal from CML to CMOS, the converted clock signal will not have a constant duty cycle since the rise time and fall time will differ. This is undesirable in crit

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