High performance chipset prefetcher for interleaved channels

Details High performance chipset prefetcher for interleaved channels High performance chipset prefetcher for interleaved channels

2008-03-25

2008-03-25

McLean, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S122000, C711S100000, C712S205000, C712S206000

Reexamination Certificate

active

07350030

ABSTRACT:
The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

REFERENCES:
patent: 6085287 (2000-07-01), O'Neil et al.
patent: 6983356 (2006-01-01), Rotithor
patent: 2004/0221111 (2004-11-01), Phelps et al.
Zhang et al., “Hardware Only Stream Prefetching and Dynamic Access Ordering”, ICS 2000.
Alexander et al., “Disrtributed Prefetch-Buffer /Cache Design for High Performance memory Systems”, In Proc. of the 2nd Intl. Symp. on High-Performance Comp. Arch., 1996.
Wei-Fen Lin et al.; Reducing DRAM latencies with an Integrated Memory Hierarchy Design; International Symposium on High-Performance computer Architecture; Jan. 2001; 12 Pages.

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