High performance capacitor

Details High performance capacitor High performance capacitor

1999-12-28

2004-10-05

Reichard, Dean A. (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S307000, C361S311000

Reexamination Certificate

active

06801422

ABSTRACT:

FIELD
The present invention relates to capacitors, and more particularly to capacitors having a high capacitance, low inductance, and low resistance.
BACKGROUND
Voltage levels on a die exhibit a droop when there is a sudden increase in demand for power on the die. This voltage droop on the die increases the switching time of the transistors on the die, which degrades the performance of the system fabricated on the die. To decrease the voltage droop during power surges, discrete decoupling capacitors are mounted adjacent to the die and connected to the conductors that provide power to the die. For a processor die, the die is mounted on a substrate, and a ring of capacitors, usually ten to fifteen two microfarad capacitors, are mounted on the substrate along the periphery of the die. These capacitors are coupled to the power supply connections at the die through lands formed on the substrate. Problems with this decoupling solution and the capacitors used to implement this solution are long standing, well known, and interrelated.
One problem with this decoupling solution is that a large number of external decoupling capacitors are required to control the voltage droop on a die. Mounting a large number of external decoupling capacitors wastes substrate real estate and reduces the die packing density on the substrate. In addition, surface area on the substrate is reserved for handling and mounting the discrete capacitors, and this reserved area is unavailable for mounting other information processing dies.
A second problem with this decoupling solution relates to the long leads needed to connect the capacitors to the power supply connections sites on the die. Power supply connection sites are usually scattered across a die. In general, it is desirable to run short leads from a power supply plane in a substrate to the power supply sites on the die. Unfortunately, with the decoupling capacitors located near the periphery of the die, long leads must be run to the power supply connection sites scattered across the die. The long leads increase the inductance and resistance of the decoupling capacitors, which tends to increase the voltage droop in response to a power surge. The long leads used to connect a die to a decoupling capacitor limit the high frequency performance of the decoupling capacitor.
A third problem is that capacitors having a large capacitance value typically have a large inherent inductance and resistance. This inherent inductance and resistance causes a large voltage droop at the die.
One solution to these problems is to fabricate a large number of capacitors on the die for decoupling the power supply connections on the die. Unfortunately, capacitors already take up a large amount of real estate on a die for a typical integrated circuit, and fabricating more capacitors on a die reduces the area available for information processing circuits.
For these and other reasons there is a need for the present invention.
SUMMARY
A capacitor comprises a plurality of conductive layers embedded in a dielectric. A plurality of vias couple at least two of the plurality of conductive layers to a plurality of connection sites.


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