High performance adaptive load output buffer with fast...

Details High performance adaptive load output buffer with fast... High performance adaptive load output buffer with fast...

2007-05-08

2007-05-08

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S027000, C326S087000

Reexamination Certificate

active

11205482

ABSTRACT:
A high performance adaptive load output buffer with fast switching of capacitive loads includes a first set of series connected complementary cascode structures having a first output node at the junction of the cascode connected p-channel device, a second output node at the junction of the two cascode structures, and a third output node at the junction of the cascode connected n-channel device. The buffer also may include at least one second set of series connected complementary cascode structures having the control terminal of the p-channel cascode structure of the second set connected to the inverted output from the first output node of first complementary cascode structure. The control terminal of the n-channel cascode structure of the second set may be connected to the inverted output from the third output node of first complementary cascode structure. The common terminal of the second cascode structure may be connected to the second output node of first complementary cascode structure and the output pad.

REFERENCES:
patent: 4992676 (1991-02-01), Gerosa et al.
patent: 6909306 (2005-06-01), El-Ayat
patent: 6924669 (2005-08-01), Itoh et al.
patent: 7126389 (2006-10-01), McRae et al.
patent: 7161376 (2007-01-01), Gallo et al.

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