High load resistance implemented in a separate polysilicon layer

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257536, 257537, 257538, 257903, H01L 2976, H01L 2974, H01L 31062, H01L 31113

Patent

active

059775980

ABSTRACT:
This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings. And, The memory cell further includes a patterned third polysilicon layer overlying the second TEOS oxide layer and in contact with the silicide for contacting the connector thereunder wherein the patterned third polysilicon layer containing dopants therein to function as a load resistor for the memory cell.

REFERENCES:
patent: 5108945 (1992-04-01), Matthews
patent: 5168076 (1992-12-01), Godinho et al.
patent: 5751050 (1998-05-01), Ishikawa et al.

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