High load driving device

Details High load driving device High load driving device

2011-07-05

2011-07-05

Crawford, Jason M (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S088000, C327S109000, C327S112000, C327S390000, C327S589000

Reexamination Certificate

active

07973564

ABSTRACT:
A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

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Lu, Chien-Yu and Chuang, Ching-Te, “Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI,” 2010 International Symposium on VLSI Design, Automation and test, Session W2-W22. Apr. 28, 2010, p. 59.
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