High level validation of designs and products

Details High level validation of designs and products High level validation of designs and products

2007-09-25

2007-09-25

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10941324

ABSTRACT:
A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario comprises a particular sequence of messages identified by the message diagram; generating a state machine operable to receive and transmit at least some of the messages identified by the message diagram according to the scenario; and testing an implementation of the design using the state machine.

REFERENCES:
patent: 5488570 (1996-01-01), Agarwal
patent: 5867494 (1999-02-01), Krishnaswamy et al.
IBM, “The Views Method and Tool”, Dec. 1, 1994, IBM—TDB, vol. 37, iss. 12, pp. 645-647.

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