Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-31
2004-02-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S014000, C703S015000, C703S016000
Reexamination Certificate
active
06687894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-level synthesis method and apparatus for automatically generating a logic circuit for a semiconductor integrated circuit (LSI) represented by a behavioral description in which processing behaviors are described, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium. More particularly, the present invention relates to a high-level synthesis method and apparatus for automatically generating an interface circuit used to interface with a bus having a predetermined protocol so as to perform data transfer with an external circuit, such as a general-purpose CPU, based on a behavioral description described in a language having a high level of abstractness, such as the C language, with the method and apparatus being used to synthesize a hard-wired circuit, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium.
2. Description of the Related Art
Recent micro processing technologies have allowed larger system LSIs. A development environment in which such system LSIs can be efficiently designed and tested is much sought after.
In the 1990s, a logic synthesis tool has been developed into practical use. Following this, a behavioral synthesis tool for synthesizing a description having a register transfer level (hereinafter referred to as an RT level) based on a behavioral description in which behaviors are described excluding information on hardware structure has been at a practical stage. The behavioral synthesis tool can generate LSI designs, comparable to those manually produced, in a shorter period of time.
When such a behavioral synthesis tool is used, a designer can concentrate his or her effort on designing an algorithm, which determines an essential behavior of an LSI, that largely relies on manual work.
At an early stage of the designing of a large digital LSI, such as a system LSI, an algorithm of an entire system is first studied and tested (this process is referred to as an “algorithm design”). Here, a software description language, such as a programming language (e.g., the “C language”), is used to design and test an algorithm on a workstation or a personal computer. Subsequently, individual processes required in a system are described with a hardware description language into behavioral descriptions which will be tested. That is, an algorithm previously described with a software description language is described again with a hardware description language into a behavioral description. Hence, conventionally, a method (high-level synthesis method) for synthesizing a circuit based on an algorithm of an entire system or behavioral descriptions using the C language has been proposed. Such a conventional technique is, for example, disclosed in Japanese Laid-Open Publication No. 10-116302, entitled “Method for Designing Integrated Circuit and Integrated Circuit Designed by the Method”.
At present, a language having a high level of abstractness, such as the “C language”, is used to describe a behavior of hardware which realizes an application, such as audio or video processing, and to synthesize a hardware circuit (high-level synthesis).
In the case of the development of a large system, a part of the processing may be implemented by software which is executed by a processor, thereby facilitating the modification of specifications or the extension of functions. In this case, a system is constructed by combining a plurality of functional blocks, such as an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit) for executing software, and a memory. In such a system, data transfer between each functional block is performed on a bus having a predetermined transfer protocol. Therefore, a bus interface circuit needs to be attached to each functional block in order to interface between the functional block and a bus.
The bus interface circuit is operated in accordance with the protocol. The bus interface circuit interprets a control signal or an address, and transfers data on a bus to a resource (memory element) in each functional block or drives desired data from each functional block and places the data on a bus. Since these behaviors are primitive compared to an application executed by each functional block, it is not efficient to describe the behaviors into behavioral descriptions and synthesize circuits corresponding to the behaviors. Further, behavioral synthesis is not recommended for interface circuits which have fixed timing. This is because the timing of the data transfer is fixed due to scheduling of behavioral synthesis in which a logic circuit is generated based on a behavioral description which lacks information on circuit structure.
Further, if a constraint relating to the timing of data transfer is added, an interface circuit can be synthesized which is compatible with its timing specification. In this case, however, a behavioral description for generating the interface circuit may be complicated, other synthesized circuit portions may have poor performance, the synthesized interface circuit may occupy a large area in an actual LSI, or the like, which are disadvantages.
To avoid this, conventionally, an interface circuit is separately designed, mainly, by manual work and attached to an application section.
FIG. 24
is a design flowchart showing such a conventional technique. As shown in
FIG. 24
, in a conventional design technique, circuit portions other than an interface circuit are synthesized in accordance with a process flow from an “behavioral description” via predetermined processes to “RT level circuit description”. However, only the interface circuit is separately designed by manual work. The “RT level circuit description” and the design of the interface circuit are combined into an “entire circuit description”.
As shown in
FIG. 24
, the aforementioned predetermined processes include: an “behavioral description analyzing section” for parsing a behavioral description in which processing behaviors are described; a “control data flow graph (hereinafter referred to as CDFG) generation section” for representing a dependence relationship between operations in the behavioral description in terms of execution order; a “scheduling section” for successively allocating time to each operation, input, and output step in CDFG; an “allocation section” for allocating an operator, a register and input and output pins required to execute a scheduled CDFG to nodes; a “data path generating section” for generating a circuit path (e.g., a multiplexer) corresponding to a data-dependent branch in a CDFG; a “controller generating section” for generating a controller which controls an operator, a register, and a multiplexer generated by allocation and data path generation. These predetermined processes are described in detail later.
In the above-described conventional technique, the interface circuit is designed by manual work. In this case, if an application is complicated and data transfer via a bus is required between a number of resources (memory elements), such as communication paths, memories, and registers, the design of interface circuits is significantly complicated for manual work and errors are likely to occur.
Further, since interface circuits are designed separately from an application, every time the application is changed and the number of resources or the type of data is changed, interface circuits need to be modified by manual work.
In most design developments of circuits, the specifications of the circuits are often changed. If inputs and outputs of a circuit are changed, the interface circuits have to be modified. Modification of circuits is a time-consuming task, resulting in extension of an increased design time.
Errors are likely to occur in manual design. Further, data transfer to and from a memory via a bus is typically performed. In conventional manual design, memory add
Ohnishi Mitsuhisa
Tanaka Shin-ichi
Birch & Stewart Kolasch & Birch, LLP
Dimyan Magid Y
Sharp Kabushiki Kaisha
Siek Vuthe
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