High level synthesis method and high level synthesis apparatus

Details High level synthesis method and high level synthesis apparatus High level synthesis method and high level synthesis apparatus

2007-03-20

2007-03-20

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10991052

ABSTRACT:
First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.

REFERENCES:
patent: 6611952 (2003-08-01), Prakash et al.
patent: 2003/0028854 (2003-02-01), Nishida et al.
patent: 5-101141 (1993-04-01), None

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