High-level synthesis method

Details High-level synthesis method High-level synthesis method

2005-08-02

2005-08-02

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06925628

ABSTRACT:
A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of the CDFG generated in the CDFG generation, expressing contents of processing, to a time synchronized with a clock called a Step, based on the CDFG and a constraint condition of the digital circuit described in a constraint file, thereby scheduling the CDFG; generating allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling, based on resource-level layout information representing a layout of the resources, and circuit information representing a connecting relationship between the resources; and outputting the circuit information generated in the allocation and circuit information generation.

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Kaneko. M., et al., “Assignment Based Approach to High Level Synthesis for NetRelevant Dsign Criteria”, in Technical Report of IEICE., VID 98-147, ICD98-293(Mar. 1999), The Institute of Electronics, Information and Communication Engineers., pp 49-56.

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