High level synthesis device, method for generating a model...

Details High level synthesis device, method for generating a model... High level synthesis device, method for generating a model...

2007-09-04

2007-09-04

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10850153

ABSTRACT:
A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

REFERENCES:
patent: 6052524 (2000-04-01), Pauna
patent: 6449750 (2002-09-01), Tsuchiya
patent: 6952816 (2005-10-01), Gupta et al.
patent: 6993469 (2006-01-01), Bortfeld
patent: 2002/0152061 (2002-10-01), Shimogori et al.
patent: 2003/0154465 (2003-08-01), Bollano et al.
patent: 10-149382 (1998-06-01), None
patent: 2001-014356 (2001-01-01), None

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