Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-15
2002-08-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06438739
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a high-level synthesis device and a high-level synthesis method, for synthesizing a circuit in accordance with a behavioral description which describes the behavior of the circuit in a high-level language, and a recording medium on which a high-level synthesis program for synthesizing a circuit in such a manner is recorded. More specifically, the present invention relates to a high-level synthesis device and a high-level synthesis method, for synthesizing a circuit in accordance with a behavioral description including a description of synchronous communications, and a recording medium on which a high-level synthesis program for synthesizing a circuit in such a manner is recorded.
BACKGROUND OF THE INVENTION
There have conventionally been some high-level synthesis methods for simulating behavior and synthesizing a circuit, in accordance with a behavioral description which describes a synchronous circuit in a language.
One of the conventional high-level synthesis methods which is employed in a behavioral synthesis system, “Behavioral Compiler” (a product name) manufactured by Synopsys, Inc., is as follows. Namely, the behavioral synthesis system synthesizes a register-transfer-level data of a circuit structure from a behavioral-level data of the circuit structure in accordance with an input of a behavioral description written in VHDL (VHSIC hardware description language) or Verilog-HDL (HDL: hardware description language).
In a synchronous circuit, a clock is generally used as a reference signal for determining the timing of the operation of the whole circuit. In partial circuits (such as an arithmetic unit and a register) which operate simultaneously, processing (individual processing) executed by the respective partial circuits are synchronized with each other by using the clock signal. Generally, in the steps of designing a circuit after the step of designing a register-transfer-level design (logic design), the timing of performing each operation in the circuit (at which time each operation should be executed) is determined with reference to the clock signal. It is thus possible to simulate the behavior using the clock signal as the reference signal.
However, in the step of designing a behavioral-level design (functional design) before the step of designing the register-transfer-level design, the behavior of the circuit is described without reference to the clock signal. Therefore, the timing of executing each operation is not determined until the circuit is synthesized. As a result, when the behavior of the circuit is simulated, asynchronous processes operating on different clocks may perform a data transfer without achieving synchronization with each other, thereby possibly losing the data.
For that reason, it is required to synchronize the asynchronous processes with each other. However, in the above conventional behavioral synthesis system, a command for achieving synchronization between the asynchronous processes cannot be used. Therefore, it is necessary to clearly describe, in the language, a protocol (communication procedure) for communicating data between the asynchronous processes, in order to perform the simulation by synchronizing the asynchronous processes with each other in the behavioral synthesis system.
In this case, the synchronization between the asynchronous processes is clearly described as a behavioral description on a behavioral level. Therefore, with reference to the behavioral description, the simulation in the step of designing the behavioral-level design can be carried out with the asynchronous processes synchronized with each other.
However, a circuit synthesized by the above conventional high-level synthesis method has the following problem. Namely, irrespective of whether synchronous communications between the partial circuits described by the behavioral description can be achieved without handshaking, synchronous communications between the asynchronous processes are realized by a circuit for performing the communications in accordance with the protocol, i.e., by a circuit for data communications between the asynchronous processes with handshaking.
Data communications using handshaking is performed in such a manner that data transmission and reception are carried out after confirming that preparation for transmitting and receiving data is completed. In addition, after finishing the transmission and reception of the data, it is confirmed that the data is properly transmitted and received. Therefore, in the circuit synthesized by the above high-level synthesis method, two control signal lines are always built between the partial circuits using handshaking, in addition to one data line provided for transmission and reception of data. Here, one of the two control signal lines is provided so that the sending side informs the receiving side that the data is ready to be transmitted and received, and the other is provided so that the receiving side informs the sending side that the data has been received. In this way, two control signal lines are always provided for handshaking, even when the synchronous communications between the partial circuits described by the behavioral description is realized without using handshaking. As a result, the circuit scale is enlarged, and the speed of data communications is decreased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-level synthesis device and a high-level synthesis method, for synthesizing a small-scale high-speed circuit in accordance with a behavioral description which includes a description of synchronous communications and enables a simulation of the synchronous communications between asynchronous processes, and a recording medium on which a high-level synthesis program for synthesizing such a circuit is recorded.
In order to achieve the above object, a high-level synthesis device of the present invention is based on a high-level synthesis device for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, and characterized in including:
a process extraction section for extracting an available process from all processes described in a behavioral description in accordance with the behavioral description including a description of synchronous communications, the available process being a process for performing data communications through a path having no loop;
a circuit synthesis section for producing partial circuits which realize respective available processes and for connecting the partial circuits with each other, in accordance with the inputted behavioral description, so as to synthesize a specific circuit; and
a delay insertion section for inserting a delay circuit into a path that connects partial circuits with each other so that data communications between the partial circuits through a plurality of paths are synchronized with each other.
With the above structure, when inputting a behavioral description including a description (command, function, and procedure) for performing synchronous communications between asynchronous processes operating at the same time, the process extraction section of the high-level synthesis device automatically extracts an available process, which can realize the synchronous communications without handshaking, from processes included in the behavioral description. When synthesizing the circuit by connecting the partial circuits that realize the respective processes, a delay circuit is inserted into a path connecting partial circuits with each other so that the data communications between the partial circuits through a plurality of paths are synchronized with each other.
With this arrangement, in the specific circuit synthesized by the high-level synthesis device, although data communications between the available processes are performed without handshaking, partial circuits realizing the respective available processes can carry out the data communications without losing data.
Do Thuan
Renner Otto Boisselle & Sklar
Sharp Kabushiki Kaisha
Smith Matthew
LandOfFree
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