Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-11
2004-12-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06832363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-level synthesis apparatus for automatically generating a logic circuit for a semiconductor integrated circuit (LSI) represented by a behavioral description (design data) in which processing behaviors of the logic circuit are described. The present invention also relates to a high-level synthesis method using the high-level synthesis apparatus, a method for producing a logic circuit using the high-level synthesis method, and a computer-readable recording medium storing a control program for carrying the high-level synthesis method.
2. Description of the Related Art
Recent micro processing technologies have allowed larger system LSIs. A development environment in which such system LSIs can be efficiently designed and tested is much sought after.
In the 1990s, a logic synthesis tool was developed into practical use. Following this, a behavioral synthesis tool for synthesizing a description having a register transfer level (hereinafter referred to as an RT level) based on a behavioral description in which only behaviors are described excluding information on hardware structure was put into use. The behavioral synthesis tool generated LSI designs, comparable to those manually produced, in a shorter period of time.
When such a behavioral synthesis tool is used, a designer can concentrate his or her efforts on designing an algorithm, which determines an essential behavior of an LSI. Such design of an algorithm largely relies on manual work. As a result, the quality of a circuit can be improved.
At an early stage of the designing of a large digital LSI, such as a system LSI, an algorithm of an entire system is first studied and tested (this process is referred to as an “algorithm design”). Here, a software description language, such as a programming language (e.g., the “C language”), is used to design and test an algorithm on a workstation or a personal computer.
Subsequently, individual processes required in a system are described with a hardware description language into behavioral descriptions which will be tested. Therefore, an algorithm previously described with a software description language is described again with a hardware description language into a behavioral description.
Hence, conventionally, a method (high-level synthesis method) for synthesizing a circuit based on an algorithm of an entire system or a behavioral description using the C language was proposed. Such a conventional technique is, for example, disclosed in Japanese Laid-Open Publication No. 10-116302, entitled “Method for Designing Integrated Circuit and Integrated Circuit Designed by the Method”.
At present, a language having a high level of abstractness, such as the “C language”, is used to describe a behavior of hardware which realizes an application, such as audio or video processing, and to synthesize a hardware circuit (high-level synthesis).
Firstly, a behavioral description language will be described. Hereinafter, the C language is extended for the purpose of behavioral description in the following description. Specifically, the extended C language includes par sentences for explicitly describing parallel operations, commands for data communication between the parallel operations, and communication channels.
An example of such a language is a Bach C language disclosed in “Bach: Environment for LSI Design with C Language”, The 11
th
Workshop on Circuits and Systems in Karuizawa, Apr. 20-21, 1998, and “Hardware Complier Bach”, TECHNICAL REPORT OF IEICE CRSY97-87 (1997-10).
FIG. 15
shows an example of the C language for hardware description. In this example, the following behavior is described.
As shown in
FIG. 15
, the third line of the behavioral description is the declaration of an int type synchronous communication channel ch.
“Par” on the sixth line is of a par sentence, which explicitly indicates parallel operations. Here, the sentence indicates that two blocks therein are operated in parallel.
The seventh line describes a first thread operation, indicating that a data communication command “send” is used to send a value
10
to the communication channel ch.
The eighth line describes the next thread operation, indicating that a data communication command “receive” is used to receive data from the communication channel ch, and substitute the received data into a variable x.
The tenth line indicates that after the par sentence on lines
6
-
9
is executed, the content of the variable x is output as an integer type decimal number to “stdout”.
Next, the processes of high-level synthesis will be explained based on an exemplary high-level synthesis as proposed by Japanese Laid-Open Publication No. 10-116302, entitled “Method for Designing Integrated Circuit and Integrated Circuit Designed by the Method”. The flow of high-level synthesis is roughly divided into four stages: (N1) to (N4). The explanation will be carried out with reference to the function blocks in FIG.
16
.
(N1) A behavioral description which describes an algorithm of the processing behavior of a circuit is analyzed.
(N2) The processing behavior is divided into threads which are asynchronously operated in parallel.
(N3) For each thread, the following processes (N3a) to (N3f) are carried out.
(N3a) Synthesis of CDFG
CDFG (control data flow graph) is a graph representing dependence relationships between computations in terms of execution order. In a CDFG, computations, inputs and outputs are represented by nodes, and data dependence relationships are represented by directed branches.
(N3b) Scheduling
A time corresponding to a clock, called a step, is allocated successively to each of the computations, the inputs and the outputs in the CDFG.
(N3c) Allocation
Computation units, registers, and input and output pins required for execution of the scheduled CDFG are generated. The computation units are allocated to the computations in the CDFG. The registers are allocated to data dependence branches across clock borders. The input and output pins are allocated to the input and the outputs.
(N3d) Generation of Data Path
Data paths corresponding to the respective data dependence relationship branches in the CDFG are generated.
(N3e) Generation of Controller
A controller for controlling the computation units, registers and multiplexers generated during the allocation and the generation of the data paths is generated.
(N3f) Generation of RT Level Circuit
A circuit description of the circuit generated by the above-described processes is generated using a hardware description language, such as VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language], and the like.
(N4) RT level circuits each for the respective threads (partial circuit) are integrated together into a single RT level circuit.
Next, the parallel operation and the communication in the high-level synthesis will be explained.
Hereinafter, it is assumed that in communication using synchronous channels (hereinafter referred to as synchronous channel communication), data is transferred after both a sender-end thread (hereinafter referred to as a send-thread) and a receiver-end thread (hereinafter referred to as a receive-thread) are in a state of readiness for communication.
As one method for realizing synchronous channel communication, a circuit configuration as shown in
FIG. 17
, which employs a handshake control signal, may be used. In such a circuit configuration, a send-thread circuit has the following ports. An (I) in the name of each port of the circuit indicates that the port is an input port, while an (O) indicates that the port is an output port. “wtx” represents a control line port for a send request signal (or a send completion signal) to a receiver end. “wrx” represents a control line port for a receive request signal (or a receive completion signal) from a receiver end. “wdata” represents a data line port at a sender end.
On the other hand, a receive-thread circuit has the following ports. An (I) in the name of each port of the circuit indicates tha
Birch & Stewart Kolasch & Birch, LLP
Lin Sun James
Siek Vuthe
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