High level (L2) cache and method for efficiently updating direct

Details High level (L2) cache and method for efficiently updating direct High level (L2) cache and method for efficiently updating direct

1996-10-07

1999-10-05

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711122, 711144, 711146, 710 39, 710 54, G06F 1208, G06F 1318

Patent

active

059639784

ABSTRACT:
A high-level (L2) cache and a efficient method for writing directory entries into an array of directory entries are disclosed. The high-level (L2) cache operates differently depending upon whether a MESI (Modified, Exclusive, Shared, Invalid) state of a cache line in Invalid or Modified when the cache line's low-level (L1) Inclusive bit is set. Initially, the high-level (L2) cache retrieves a directory entry from the array of directory entries. This directory entry is placed into an n-position priority queue. Associated with the n-position priority queue is a set of priority indicators. These priority indicators are updated when a directory entry is placed into the n-position priority queue to indicate which order the various directory entries were placed into the n-position priority queue. If the directory entry is waiting for results to be received from the system bus, the directory entry will remain in the queue until such results are received. If the directory entry is not waiting for results to be received, it will be written back to the array of directory entries. For the directory entries waiting upon results to be received, those entries will be modified using information contained in the results, then written to the array of directory entries. The high-level (L2) cache can also resolve collisions between a processor request and a system request originating from another computing unit. If a system request would not alter a line in the low-level (L1) cache, the high-level (L2) cache will wait until the system request finishes accessing a shared resource to process the processor request, thereby avoiding the sending of a RETRY signal to the processor.

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