High isolation, low power high speed multiplexer circuit

Details High isolation, low power high speed multiplexer circuit High isolation, low power high speed multiplexer circuit

1999-06-11

2003-10-21

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C327S407000

Reexamination Certificate

active

06636077

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates, generally, to multiplexer circuits useful in the context of high speed data switches and, more particularly, to a multiplexer circuit topology which yields high isolation of the deselected channels, thereby reducing jitter at high switching speeds while at the same time reducing power consumption.
2. Background Art and Technical Problems
The increasing proliferation of high speed data traffic in both long-haul and short-haul communication networks requires increasingly reliable high speed crosspoint switches. Crosspoint switches are particularly valuable in that they enable the communication network to be reconfigured to accommodate changing traffic requirements and response to high-priority messages. High speed crosspoint switches are also increasingly being cascaded together to form larger and larger high speed switching networks.
As the switching speed and complexity of high speed communication networks continues to increase, jitter becomes increasingly problematic. Presently known attempts to limit the jitter associated with these switches impedes the speed of the switch or the ability of the switch to broadcast any input to multiple outputs when required.
High speed crosspoint switches are thus needed which minimize jitter, while at the same time reduce cross talk between the channels on the chip.
SUMMARY OF THE INVENTION
In accordance with an exemplary embodiment of the present invention, a two stage multiplexer circuit is provided having a buffer stage and a multiplexer stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.
In accordance with a particularly preferred embodiment, a dedicated differential buffer is associated with each input channel. An active channel receives power and suitably provides a selected signal to the output of the switch. The inactive channels and their associated buffers are suitably de-powered such that enhanced isolation of the deselected buffers with respect to the output terminal may be achieved. Moreover, by powering down the deselected channels, the multiplexer circuit consumes substantially less power than presently known switches.
In accordance with a further aspect of the present invention, a high isolation, low power multiplexer circuit may be conveniently implemented in aluminum gallium arsenide/gallium arsenide (AlGaAs/GaAs) HBT IC technology available from the Connexant corporation of Newberry Park, Calif. Alternatively, the invention may be suitably implemented with any form of bipolar or high speed MOS technology.


REFERENCES:
patent: 5172011 (1992-12-01), Leuthold et al.
patent: 5959491 (1999-09-01), Kang
“Differential Emitter Dotted Multiplexor”, IBM Technical Disclosure Bulletin, vol. 37, No. 2A, Feb. 1, 1994, p. 177-178.

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