High integrity recovery from multi-bit data failures

Details High integrity recovery from multi-bit data failures High integrity recovery from multi-bit data failures

2005-09-20

2005-09-20

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006130

Reexamination Certificate

active

06948091

ABSTRACT:
Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

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