Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-28
2001-05-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S627000, C438S687000, C438S688000
Reexamination Certificate
active
06232223
ABSTRACT:
TECHNICAL FIELD
The present invention relates to high density, multi-metal layer semiconductor devices having interconnection patterns with highly reliable borderless vias. The invention has particular applicability in manufacturing high density multi-metal layer semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum (Al) or an Al alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as a spin-on-glass (SOG), is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature.
The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of real estate on a semiconductor chip, which is antithetic to escalating requirements for high densification. In addition, the reduction in design features to about 0.25 microns and under necessitates openings with very high aspect ratios (height/diameter), e.g. greater than about 4. As the aspect ratio of openings increases, the difficulty in depositing a barrier layer lining in the opening, as by conventional sputtering techniques, increases significantly. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result. misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a “borderless via”, which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the gap filling layer is penetrated by etching when forming a through-hole, due to the low density and poor stability of conventional filling materials, such as SOG. As a result of such penetration, moisture and gas accumulate, thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate causing a short. The use of borderless vias is also problematic in that a side surface of a metal feature is exposed to etching during formation of the through-hole.
In U.S. Pat. No. 5,619,072, a borderless via is disclosed wherein a metal feature is provided with sidewall spacers to alleviate the spiking problem. In copending application Ser. No. 08/924,131, filed on Sep. 5, 1997, a titanium nitride barrier layer is deposited by CVD to prevent undercutting of the side surface of the underlying metal feature in a borderless via.
As the aspect ratios of a through-hole increase, however, and metal features are scaled further, it becomes increasingly difficult to satisfactorily deposit a barrier layer on the side surface of a metal feature. Conventional metal features comprise a primary conductive layer of Al. Conductive plugs are typically comprised tungsten deposited from tungsten hexafluoride (WF
6
) vapor which undesirable reacts with Al. This problem is illustrated in
FIG. 1
wherein metal feature
11
is formed on insulating layer
10
. Metal feature
11
is part of a patterned metal layer typically comprising a lower metal layer e.g., titanium (Ti) or W, (not shown), primary intermediate metal layer
11
A, such as Al, and an upper anti-reflective coating (ARC)
11
B, such as titanium nitride (TiN). Second dielectric layer
12
is formed on the patterned metal layer and through-hole
13
is formed therein, as by anisotropic etching. Through-hole
13
is intentionally misaligned, thereby exposing a portion
11
B and a side surface
112
of metal feature
11
. Side surface
112
is typically etched upon forming through-hole
13
forming an undercut portion in the form of a cavity. The difficulty in depositing a barrier layer on the undercut concave portion prior to filling the through-hole under such circumstances becomes acutely problematic. Barrier layer
14
, typically TiN, does not uniformly cover the cover side surface
112
, as shown by discontinuity
15
. Accordingly, during deposition of W to fill the through-hole, as with conventional vapor deposition employing WF
6
, Al reacts violently with WF
6
resulting in an unreliable interconnection.
Accordingly, there exists a need for methodology enabling the formation of a reliable borderless via, particularly when filling high aspect ratio openings. There exist a particular need for methodology enabling the formation of a reliable borderless via while avoiding interaction of the plug filling material with an underlying metal feature.
DISCLOSURE OF THE INVENTION
An object of the present invention is a high density multilevel semiconductor device with an interconnection pattern comprising highly reliable borderless vias.
Another object of the present invention is a method of manufacturing a high density multi-metal layer semiconductor device with design features of 0.25 microns with an interconnection pattern comprising highly reliable borderless vias.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a semiconductor device comprising: a first dielectric layer on a substrate; a first patterned metal layer, comprising a metal feature with an upper surface and first and second side surfaces, on the first dielectric layer; a capping layer comprising: a first portion on a first part of the upper surface and on the first side surface of the metal feature; and a second portion, spaced apart from the first portion, forming a sidewall spacer on the second side surface of the metal feature; a second dielectric layer formed on the patter
Mehta Sunil D.
Tran Khanh Q.
Advanced Micro Devices , Inc.
Bowers Charles
Pham Thanhha
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