Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2001-06-19
2002-11-19
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S085000, C326S113000, C327S170000
Reexamination Certificate
active
06483340
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit to be loaded in a semiconductor integrated circuit device, and particularly to an output buffer circuit in which the output transistors are divided.
2. Description of the Related Art
Conventionally, such types of output buffer circuits in which the output transistors are divided have been proposed variously.
FIG. 1
is a circuit diagram showing an example of a conventional output buffer circuit. As shown in
FIG. 1
, a conventional output buffer circuit
500
comprises an output transistor section
510
and an inverter
540
,
550
. The output transistor section
510
comprises an inverter
520
and an inverter
530
connected in parallel. The inverter
520
comprises a PMOS transistor (hereinafter referred to as a PMOS)
521
and a NMOS transistor (hereinafter referred to as a NMOS)
522
having channel widths which satisfy a desired driving capability. Also, the inverter
530
comprises a PMOS
531
and a NMOS
532
. The channel widths of the PMOS
531
and the NMOS
532
are narrower than those of the PMOS
521
and the NMOS
522
. Furthermore, an input terminal of the inverter
520
is connected to an output terminal N
504
of the inverter
540
, and an input terminal of the inverter
530
is connected to an output terminal N
505
of the inverter
550
.
Both of the output terminals of the inverters
520
,
530
are connected to an output terminal N
503
of the output buffer circuit
500
. Also, both of the input terminals of the inverters
540
,
550
which drive the inverters
520
,
530
, respectively, are connected to an input terminal N
2
of the output buffer circuit
500
. Furthermore, the inverters
540
,
550
consist of transistors having generally the same sizes.
Also, an example of another conventional output buffer circuit is disclosed in Japanese Patent Publication Laid-Open No. Hei 11-191729 (hereinafter referred to as the prior art).
FIG. 2
is a circuit diagram showing an output buffer circuit disclosed in the prior art. As shown in
FIG. 2
, transistors PMOS
624
a
,
626
a
and NMOS
624
b
,
626
b
of output final stages divided into at least two are provided in an output buffer circuit
610
disclosed in the prior art. Also, a transistor PMOS
618
a
for current-voltage limiting is provided between a gate of the PMOS
624
a
and a gate of the PMOS
626
a
, and a transistor NMOS
618
b
for current-voltage limiting is provided between a gate of the NMOS
624
b
and a gate of the NMOS
626
b
. Also, driving circuits
616
a
,
616
b
for driving the PMOS
624
a
and the NMOS
624
b
respectively, in response to potential of an internal signal line
632
are connected to each gate of the PMOS
624
a
and the NMOS
624
b
. In addition, gates of the transistors PMOS
626
a
, NMOS
626
b
are connected with potential compensation circuits
622
a
,
622
b
for compensating the potential of the gate thereof.
In the output buffer circuit
610
, when each transistor of the output final stage becomes ON, the driving circuits
616
a
,
616
b
drive a gate end of one transistor of the output final stage and at the same time, drive a gate end of another transistor of the output final stage via the transistor for current-voltage limiting, thereby controlling the slew rate of current to suppress the generation of noise and perform high speed operation.
In the conventional output buffer circuit structure in general, for example, if the slew rate standard becomes strict, as in an output buffer circuit for PCI (Peripheral Component Interconnect), then fluctuation in the manufacturing process can have a great effect, and it is very difficult to satisfy the slew rate standard according to conditions such as temperature, power supply voltage, etc.
For example, in the above described output buffer circuit
500
shown in
FIG. 1
, when adjustment of the slew rate of the signal of the output terminal N
503
is desired, it is necessary to blunt the output waveforms of the inverters
540
,
550
. However, if the output waveforms of the inverters
540
,
550
become blunt, then the influence on the output waveforms of the inverters
540
,
550
becomes great when a channel length L and threshold voltage (hereinafter, referred to as V
TH
) of the transistor have changed, and at the same time, the influence is added to variations of the PMOS
521
,
531
and the NMOS
522
,
532
of the output transistor sections and appears at a signal OUT of the output terminal N
503
.
Also, in the output buffer circuit
610
of
FIG. 2
disclosed in the prior art, the stability of rise time, fall time and signal delay time, etc. of the output signal of an output pad
634
depends on the channel length L and V
TH
of the final stage transistors PMOS
624
a
,
626
a
and NMOS
624
b
,
626
b
, and depends as well on the driving capability of the driving circuits
616
a
,
616
b
for supplying a signal to the gate end of each of the above-described transistors and the channel length L and V
TH
of transistors PMOS
620
a
,
628
b
and NMOS
620
b
,
628
a
. Accordingly, fluctuation in the manufacturing process is reflected in the channel length L and V
TH
of the final stage transistors PMOS
624
a
,
626
a
and NMOS
624
b
,
626
b
, as well as in the driving capability of the driving circuits
616
a
,
616
b
and the channel length L and V
TH
of the transistors PMOS
620
a
,
628
b
and NMOS
620
b
,
628
a
, such that the stability of output operation of the output pad
634
can not be ensured.
FIG. 3
is a schematic waveform diagram showing the change in the output signal upon rising in the conventional output buffer circuit. In
FIG. 3
, a line W
fast
represents the slew rate under a condition that the rising is fast in the conventional output buffer circuit, a line W
slow
represents the slew rate under a condition that the rising is slow, a line W
max
represents the maximum slew rate permissible in the PCI, and a line W
min
represents the minimum slew rate permissible in the PCI. As shown in
FIG. 3
, the slew rate represented by the line W
fast
, is greater than the slew rate represented by the line W
max
. As such, in the case of the output buffer circuits shown in
FIGS. 1 and 11
, there is a problem that the rise time Tr and the fall time Tf of the output signal deviate from the value specified by the PCI standard, according to conditions such as temperature, power supply voltage, etc.
Also, the conventional output buffer circuit
610
shown in
FIG. 2
, is problematic, in that PMOS
618
a
,
620
a
,
628
b
, NMOS
618
b
,
620
b
,
628
a
, inverters
630
a
,
630
b
are needed in addition to the general driving circuits
616
a
,
616
b
, such that layout size becomes large and the circuit structure becomes complicated.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an output buffer circuit having a divided output transistor, wherein the influence of characteristic variations due to manufacturing process fluctuation and the influence of conditions from change in use such as temperature, power supply voltage are suppressed, and at the same time, a circuit structure is simplified and miniaturized, so that high integration is possible.
An output buffer according to the present invention comprises an output transistor section, and the output transistor section includes an output terminal, a first and a second transistors of the first conductive type of which each one end of source-drain line is connected to a high potential power supply and other end thereof is connected to said output terminal, and a first and a second transistor of the second conductive type of which each one end of source-drain line is connected to a low potential power supply and other end thereof is connected to said output terminal. Also, said output buffer circuit comprises a first transfer gate including a first input terminal to which input signal is inputted and a first driving output terminal to be connected to a gate of said first transistor of the first conductive type an
Chang Daniel D.
Hayes & Soloway P.C.
NEC Corporation
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