High impedance test mode for JTAG

Details High impedance test mode for JTAG High impedance test mode for JTAG

1995-12-19

1997-05-20

Beausoliel, Jr., Robert W.

Excavating

371 225, G01R 3128

Patent

active

056319126

ABSTRACT:
A specially configured JTAG test circuit allows multiple bus connections within an integrated circuit chip to be selectively placed in a high impedance state in an efficient manner. The output enable shift register locations are placed in close logical proximity to one another along the JTAG data shift register boundary scan path so that data bits need not be shifted into all of the data shift register locations within the integrated circuit chip in order to selectively enable and disable the several bus interfaces within the integrated circuit chip. In this manner, the integrated circuit chip may be isolated from selected ones of the buses connected to the integrated circuit chip, while other bus connections can remain enabled to drive others of the buses connected to the integrated circuit chip. Thus, problems associated with setting the entire integrated circuit chip in a high impedance mode are avoided.

REFERENCES:
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5153882 (1992-10-01), Lyon et al.
patent: 5210759 (1993-05-01), DeWitt et al.
patent: 5514975 (1996-05-01), Sartwell et al.
Maunder, et al., "IEEE Standard Test Access Port and Boundary-Scan Architecture", Institute of Electrical and Electronics Engineers, Inc., Oct. 21, 1993, pp. iii-A-12.

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