Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1995-02-03
2001-02-13
Ngô, Ngân (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S536000, C257S537000, C257S757000, C257S761000, C257S904000
Reexamination Certificate
active
06188112
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to high impedance load devices.
2. Description of the Prior Art
CMOS static random access memory (SRAM) are increasingly used in the electronics industry due to their combination of speed, low power, and no requirements for refresh. A CMOS SRAM cell is built around a cross-coupled latch and accessed, typically, by two control gates for a standard SRAM cell. The basic SRAM cell may be formed using cross-coupled CMOS inverters, each having two n-channel and p-channel transistors. The p-channel transistors often are replaced with resistive loads. Typical loads presently used include a polycrystalline silicon resistor or a pn junction formed by two back-to-back polycrystalline silicon diodes. These types of resistive loads still take up large amounts of physical layout space.
With the desire to increase the density of integrated circuit devices on silicon, it would be desirable to decrease the physical layout space required by resistive loads such as polycrystalline silicon resistors and p-n junctions. Therefore, it would be desirable to provide a highly resistive polycrystalline resistive structure that requires less physical layout space than the presently used resistive load devices.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a high impedance load device in an integrated circuit. An opening in an insulating layer is formed to expose a first region below the insulating layer. A layer of a refractory metal silicide is formed in the opening. The refractory metal silicide contains an excess of silicon. Then, the integrated circuit is annealed until a layer of epitaxial silicon from the refractory metal silicide is grown, called solid phase epitaxy (SPE), on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide layer.
The method of the present invention may be used to create high impedance load devices in integrated circuit. For example the present invention may be use in a static random access memory (SRAM) in an integrated circuit. The SRAM includes a pass gate transistor; a pull-down transistor, wherein the pull-down transistor shares a source/drain region with the pass gate transistor; an insulating layer covering the two transistors; an opening in the insulating layer over the shared source/drain region; a region of a refractory metal silicide in the opening; and an epitaxial silicon layer deposited from the refractory metal silicide between the region of refractory metal silicide and the source/drain region, wherein the epitaxial silicon layer results from annealing the integrated device.
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Galanthay Theodore E.
Jorgenson Lisa K.
Ngo Ngan
STMicroelectronics Inc.
Venglarik Dan
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