Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1990-04-06
1991-11-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Differential sensing
365190, G11C 700
Patent
active
050653679
ABSTRACT:
In an array of sense amplifiers associated respectively columns of a matrix array of memory cells, each amplifier comprises a first transistor having a source-drain current path connected at one end to a first output terminal and a gate connected to first ends of the memory cells of the associated column, a second transistor having a source-drain current path connected at one end to a second output terminal and a gate connected to second ends of the memory cells of the associated column. A third transistor is provided in each amplifier for grounding the other ends of the source-drain current paths of the first and second transistors when the associated column is identified by a column address during a read cycle to cause them to respond to complementary voltages supplied from a memory cell of the associated column. Fourth and fifth transistors are provided for grounding the gate electrodes of the first and second transistors when the associated column is not identified by the column address signal during the read cycle to prevent the first and second transistors from responding to voltages supplied from a memory cell of the associated column.
REFERENCES:
patent: 4504748 (1985-03-01), Oritani
NEC Corporation
Popek Joseph A.
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