Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-05-28
2001-01-23
Mai, Son (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S086000
Reexamination Certificate
active
06177807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high speed data transmission systems, and more particularly to a high speed memory including a stub at a variable end position.
2. Background Art
Very high speed SRAM and DRAM memories have synchronization problems between control signals and data signals. Phase locked loops and digital locked loops are not adequate at such high speed operation.
U.S. Pat. No. 5,457,406 issued Oct. 10, 1995 to Takada et al. entitled “Bidirectional Signal Transmission Circuit and Terminator” discloses a bidirectional signal transmission circuit in which the transmitter circuit of the logic circuit elements used in the conventional single end transmission circuit can be utilized by setting an impedance of an end circuit to be a value greater than a characteristic impedance of a transmission path, by shortening a length of the transmission path for connecting the end circuit with the logic circuit elements, and by increasing am amplitude of an input signal with utilization of a reflection wave produced by an impedance mismatching, such a signal transmission circuit where various types of transmission circuits such as a bidirectional signal transmission circuit and a single end transmission circuit are employed in a mixture form, can be made compact, and low power consumption can be achieved.
U.S. Pat. No. 5,334,962 issued Aug. 2, 1994 to Higgins et al. entitled “High-Speed Data Supply Pathway Systems” discloses a high speed data pathway system used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit ship carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.
U.S. Pat. No. 4,414,840 issued Nov. 8, 1983 to Zasio entitled “CMOS Circuit Using transmission Line Interconnections” discloses a CMOS output circuit for an integrated circuit chip used in high speed computers is designed so that it can drive transmission line interconnects to thereby increase the speed of the transfer of signals between chips. The CMOS circuit can drive either a nonterminated transmission line, a terminated transmission line or a random wire. The output circuit enables both low power consumption and high speed to be achieved.
U.S. Pat. No. 3,660,675 issued May 2, 1972 to Andrews, Jr. entitled “Transmission Line Series Termination Network For Interconnecting High Speed Logic Circuits” discloses a series termination network that interconnects high speed logic circuits in a transmission line system for transmitting binary ONE and binary ZERO information. When the logic circuit drives the transmission line to a high voltage state, a first impedance branch of the termination network applies a voltage whose magnitude approximates one half of the magnitude of voltage which defines a binary “ONE”. When the logic circuit switches the line to a low voltage state, corresponding to a binary ZERO, the network through a second impedance branch terminates the line in its characteristic impedance.
SUMMARY OF THE INVENTION
An object of the present invention is to provide apparatus for high speed memory operation to achieve high speed synchronization between control signals and data signals.
Another object of the present invention is to provide apparatus for high speed memory operation to ensure valid data at high clock rates.
Still another object of the present invention is to provide a high speed memory including a stub having a short at an end position that is incrementally variable.
A still further object of the present invention is to provide a stub having an opening at an end position that is incrementally variable.
Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings which are incorporated in and constitute a part of this invention and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 3660675 (1972-05-01), Andrews, Jr.
patent: 4124887 (1978-11-01), Johnson et al.
patent: 4414840 (1983-11-01), Zasio
patent: 5334962 (1994-08-01), Higgins et al.
patent: 5457406 (1995-10-01), Takada et al.
patent: 5504689 (1996-04-01), Fiebrich et al.
patent: 5544047 (1996-08-01), Appel
patent: 5990701 (1999-11-01), Starr
patent: 6014037 (2000-01-01), Gabara et al.
Bertin Claude L.
Fifield John A.
Hedberg Erik L.
Houghton Russell J.
Tonti William R.
Goodwin John J.
International Business Machines - Corporation
Mai Son
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